LTC2252 Datasheet, PDF (14/24 Pages) Linear Technology – 12-Bit, 125/105Msps Low Power 3V ADCs

LTC2253/LTC2252
APPLICATIO S I FOR ATIO
to set the DC input level or as a reference level to an op amp
differential driver circuit. The V_CM pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2253/LTC2252 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and input
reactance can influence SFDR. At the falling edge of CLK,
the sample-and-hold circuit will connect the 3.5pF
sampling capacitor to the input pin and start the sampling
period. The sampling period ends when CLK rises, holding
the sampled input on the sampling capacitor. Ideally the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F_ENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2253/LTC2252 being driven by an
RF transformer with a center tapped secondary. The
secondary center tap is DC biased with V_CM, setting the
ADC input signal at its optimum DC level. Terminating on
the transformer secondary is desirable, as this provides a
common mode path for charging glitches caused by the
sample and hold. Figure 3 shows a 1:1 turns ratio trans-
former. Other turns ratios can be used if the source
impedance seen by the ADC does not exceed 100Ω for
each ADC input. A disadvantage of using a transformer is
the loss of low frequency response. Most small RF
transformers have poor performance at frequencies
below 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
14
frequency input response; however, the limited gain band-
width of most op amps will limit the SFDR at high input
frequencies.
Figure 5 shows a single-ended input circuit. The imped-
ance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
V_CM
0.1µF T1
ANALOG
1:1
INPUT
25Ω
25Ω 0.1µF
25Ω
T1 = MA/COM ETC1-1T ^25Ω
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2.2µF
A_IN+
12pF
LTC2253/
LTC2252
A_IN–
22532 F03
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
V_CM
ANALOG
INPUT
HIGH SPEED
DIFFERENTIAL
AMPLIFIER 25Ω
++
CM
––
25Ω
2.2µF
A_IN+
12pF
LTC2253/
LTC2252
A_IN–
22532 F04
Figure 4. Differential Drive with an Amplifier
ANALOG
INPUT
0.1µF
1k 1k
25Ω
V_CM
2.2µF
A_IN⁺
12pF
LTC2253/
LTC2252
25Ω
A_IN^–
0.1µF
22532 F05
Figure 5. Single-Ended Drive
22532fa