LTC1755_15 Datasheet, PDF (14/16 Pages) Linear Technology – Smart Card Interface

LTC1755/LTC1756
APPLICATIO S I FOR ATIO
Overtemperature Fault Protection
An overtemperature circuit disables the chip and activates
the ALARM pin if the IC’s junction temperature exceeds
150°C.
deactivation sequence. Once PWR is brought high the built-
in deactivation sequence occurs as shown in Figure 7.
In the event of a fault, the LTC1755/LTC1756 automatically
implement the built-in deactivation sequence.
Self-Start Mode
By connecting the CARD pin to the PWR pin, the LTC1755/
LTC1756 can be made to start up automatically when a
Smart Card is detected (Figure 6). In this mode, the READY
pin becomes an interrupt signal indicating to the micro-
controller that a Smart Card is present and that V_CC, the
charge pump voltage, is at its final value. The Smart Card
remains powered as long as it is detected by the PRES pin.
When the Smart Card is removed the LTC1755/LTC1756
will automatically be deactivated by the fault detection
circuitry.
Deactivation Sequence
For maximum flexibility the Smart Card can be deactivated
either manually or automatically. In manual mode the de-
activation is controlled by explicitly manipulating the
LTC1755/LTC1756 input and control pins (DATA, AUX1IN,
AUX2IN, RIN and CIN followed by PWR and CS). In auto-
matic mode the PWR pin is used to perform the built-in
CARD
PWR
READY
TO
MICROCONTROLLER
1755 F06
Figure 6. Self-Start Mode
PC Board Layout
For best performance, the V_IN and V_CC capacitors should
be placed as close to the LTC1755/LTC1756 as possible.
This will help reduce ringing due to inductance on the V_IN
and V_CC pins that could cause problems with the LTC1755/
LTC1756 control circuitry or Smart Card. Figure 8 illus-
trates a possible layout technique using only a single layer
of the PC board.
State Definitions
IDLE/DEACTIVATION
V_CC, RST, CLK, I/O AUX2, AUX1 = L
READY, ALARM, DATA, AUX2IN, AUX1IN = Z
CARD = PRES ⊕ NC/NO
Once the LTC1755/LTC1756 enter the Idle/Deactivation
state the deactivation sequence begins. The deactivation
sequence will continue until V_CC is discharged to approxi-
mately 1V. An activation command (PWR = 0V) will only be
acknowledged once this occurs.
ALARM/DEACTIVATION
Same as Idle/Deactivation except:
ALARM = L
DEACTIVATION DIRECTIVE
V_CC
RST
RST = R_IN
CLK
CLK = C_IN
I/O
AUX2
AUX1
I/O = DATA
1755 F07
Figure 7. Deactivation Sequence
14
GND
V_IN
V_CC
17556 F08
Figure 8. Optimum Bypass Capacitor Placement