LT1993-10 Datasheet, PDF (14/16 Pages) Linear Technology – 700MHz Low Distortion, Low Noise Differential Amplifi er/ADC Driver (AV = 10V/V)

LT1993-10
APPLICATIO S I FOR ATIO
0.1mF
IF IN
80.69
0.1mF
13 _–INB 2
14 _{–INA VOCM}
6
109
+OUTFILTERED
LT1993-10
109
15
–OUTFILTERED
+INB
7
16 _+INA
3V
11k
1.9V
4.02k
31 1.5V
V_CM
1 _AIN+
LTC22xx
2 ^AIN–
199310 F09
Figure 9. Level Shifting 3V ADC V_CM Voltage for
Improved SFDR
Large Output Voltage Swings
The LT1993-10 has been designed to provide the 3.2V_P-P
output swing needed by the LTC1748 family of 14-bit
low-noise ADCs. This additional output swing improves
system SNR by up to 4dB. Typical performance curves
and AC specifications have been included for these
applications.
Input Bias Voltage and Bias Current
The input pins of the LT1993-10 are internally biased to
the voltage applied to the V_OCM pin. No external biasing
resistors are needed, even for AC-coupled operation. The
input bias current is determined by the voltage difference
between the input common mode voltage and the V_OCM pin
(which sets the output common mode voltage). At both
the positive and negative inputs, any voltage difference is
imposed across 100Ω, generating an input bias current.
For example, if the inputs are tied to 2.5V with the V_OCM
pin at 2.2V, then a total input bias current of 3mA will flow
into the LT1993-10’s +INA and +INB pins. Furthermore,
an additional input bias current totaling 3mA will flow into
the –INA and –INB inputs.
Application (Demo) Boards
The DC800A Demo Board has been created for stand-alone
evaluation of the LT1993-10 with either single-ended or
differential input and output signals. As shown, it accepts
a single-ended input and produces a single-ended output
so that the LT1993-10 can be evaluated using standard
laboratory test equipment. For more information on this
Demo Board, please refer to the Demo Board section of
this datasheet.
There are also additional demo boards available that
combine the LT1993-10 with a variety of different Linear
Technology ADCs. Please contact the factory for more
information on these demo boards.
PACKAGE DESCRIPTIO
3.50 ± 0.05
1.45 ± 0.05
2.10 ± 0.05 ^{(4 SIDES)}
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 ±0.05
3.00 ± 0.10
(4 SIDES)
PIN 1
TOP MARK
(NOTE 6)
0.75 ± 0.05
BOTTOM VIEW—EXPOSED PAD
R = 0.115
TYP
15 16
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
0.40 ± 0.10
1
1.45 ± 0.10
2
(4-SIDES)
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
14
0.200 REF
0.00 – 0.05
(UD16) QFN 0904
0.25 ± 0.05
0.50 BSC
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
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