LTC3524_15 Datasheet, PDF (13/16 Pages) Linear Technology – Adjustable TFT Bias Supply with WLED Driver

LTC3524
APPLICATIONS INFORMATION
and VH should be at least 0.47μF. Please be certain that
the capacitors used are rated for the maximum voltage
with adequate safety margin. Refer to Table 2 for a listing
of capacitor vendors.
Table 2. Capacitor Vendor Information
Supplier
Phone
Website
AVX
[phone]
www.avxcorp.com
Murata
[phone]
www.murata.com
Samsung
[phone]
www.sem.samsung.com
Taiyo Yuden
[phone]
www.t-yuden.com
TDK
[phone]
www.component.tdk.com
Printed Circuit Board Layout Guidelines
High-speed operation of the LTC3524 demands care-
ful attention to PCB layout. You will not get advertised
performance with a careless layout. Figure 4 shows the
recommended component placement for a double layer
PCB. The bottom layer is used as a common ground plane
except for the VN trace.
LAYOUT NOTES:
LIGHT GREY TOP LAYER
VIA TO BOTTOM GROUND PLANE.
GROUND PLANE FILLS BOTTOM
*KEEP R_PROG AWAY FROM SW2 TRACES
GND
V_IN
R1
L1
V_OUT
ELCD ELED1 ELED2
L2
SCHOTTKY DIODE
*
ELED1 PROG ELED2 SW2 VLED LED1
24
23
22
21
20
19
ELCD
1
VIN
2
FBVO
3
VOUT
4
SW1
5
C2–
6
TOP VIEW
COMPONENT AND IC SIZES
NOT TO SCALE
GND
GND
LED2
18
–
CH
17
+
CH
16
VH
15
FBH
14
FBN
13
C2+
V2x VNIN CN+
NC
VN
7
8
9
10
11
12
WHITE LEDs
WHITE LEDs
VH
SCHOTTKY
DIODE
VN
3524 F04
Figure 4. Suggested Layout Two Layer Board (Not to Scale)
3524f
13