LTC3440 Datasheet, PDF (13/20 Pages) Linear Technology – Micropower Synchronous Buck-Boost DC/DC Converter

LTC3440
APPLICATIO S I FOR ATIO
Output Voltage > 4.3V
A Schottky diode from SW to V_OUT is required for output
voltages over 4.3V. The diode must be located as close to
the pins as possible in order to reduce the peak voltage on
SW2 due to the parasitic lead and trace inductance.
Input Voltage > 4.5V
For applications with input voltages above 4.5V which
could exhibit an overload or short-circuit condition, a 2Ω/
1nF series snubber is required between the SW1 pin and
GND. A Schottky diode such as the Phillips PMEG2010EA
or equivalent from SW1 to V_IN should also be added as
close to the pins as possible. For the higher input voltages
V_IN bypassing becomes more critical, therefore, a ceramic
bypass capacitor as close to the V_IN and GND pins as
possible is also required.
Operating Frequency Selection
There are several considerations in selecting the operating
frequency of the converter. The first is, what are the
sensitive frequency bands that cannot tolerate any spec-
tral noise? For example, in products incorporating RF
communications, the 455kHz IF frequency is sensitive to
any noise, therefore switching above 600kHz is desired.
Some communications have sensitivity to 1.1MHz and in
that case a 2MHz converter frequency may be employed.
Other considerations are the physical size of the converter
and efficiency. As the operating frequency goes up, the
inductor and filter capacitors go down in value and size.
The trade off is in efficiency since the switching losses due
to gate charge are going up proportional with frequency.
Additional quiescent current due to the output switches
GATE charge is given by:
Buck: 500e^–12 • V_IN • F
Boost: 250e^–12 • (V_IN + V_OUT) • F
Buck/Boost: F • (750e^–12 • V_IN + 250e^–12 • V_OUT)
where F = switching frequency
Closing the Feedback Loop
The LTC3440 incorporates voltage mode PWM control.
The control to output gain varies with operation region
(Buck, Boost, Buck-Boost), but is usually no greater than
15. The output filter exhibits a double pole response is
given by:
f_{FILTER_POLE} = _{2 • π •}
1
Hz (in Buck mode)
L • C_OUT
f_{FILTER_POLE} = _{2π •}
V_IN
L • V_OUT
Hz (in Boost mode)
where C_OUT is the output filter capacitor.
The output filter zero is given by:
f_{FILTER_ ZERO}
=
2
•
π
1
• R_ESR
• C_OUT
Hz
where R_ESR is the capacitor equivalent series resistance.
A troublesome feature in Boost mode is the right-half
plane zero (RHP), and is given by:
f_RHPZ
=
V_IN2
2 • π •I_OUT • L• V_OUT
Hz
The loop gain is typically rolled off before the RHP zero
frequency.
A simple Type I compensation network can be incorpo-
rated to stabilize the loop but at a cost of reduced band-
width and slower transient response. To ensure proper
phase margin, the loop requires to be crossed over a
decade before the LC double pole.
The unity-gain frequency of the error amplifier with the
Type I compensation is given by:
f_UG
=
2
•
π
1
Hz
• R1• CP1
Most applications demand an improved transient response
to allow a smaller output filter capacitor. To achieve a
higher bandwidth, Type III compensation is required. Two
zeros are required to compensate for the double-pole
response.
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