LTC3417A-2 Datasheet, PDF(13/20 Page) Linear Technology – Dual Synchronous 1.5A/1A 4MHz Step-Down DC/DC Regulator

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LTC3417A-2 Datasheet, PDF (13/20 Pages) Linear Technology – Dual Synchronous 1.5A/1A 4MHz Step-Down DC/DC Regulator

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LTC3417A-2

APPLICATIONS INFORMATION

VRUN

2V/DIV

VOUT

1V/DIV

1A/DIV

VIN = 3.6V

VOUT = 1.8V

RL = 0.9Î©

200Î¼s/DIV

3417A-2 F02

Figure 2. Digital Soft-Start OUT1

Soft-Start

Soft-start reduces surge currents from VIN by gradu-

ally increasing the peak inductor current. Power supply

sequencing can also be accomplished by controlling the

ITH pin. The LTC3417A-2 has an internal digital soft-start

for each regulator output, which steps up a clamp on

ITH over 1024 clock cycles, as can be seen in Figures 2

and 3. As the voltage on ITH ramps through its operating

range, the internal peak current limit is also ramped at a

proportional linear rate.

Mode Selection

The SYNC/MODE pin is a multipurpose pin which provides

mode selection and frequency synchronization. Connect-

ing this pin to VIN enables Burst Mode operation for both

regulators, which provides the best low current efï¬ciency

at the cost of a higher output voltage ripple. When SYNC/

MODE is connected to ground, pulse skipping operation

is selected for both regulators, which provides the low-

est output voltage and current ripple at the cost of low

current efï¬ciency. Applying a voltage that is more than

1V from either supply results in forced continuous mode

for both regulators, which creates a ï¬xed output ripple

and allows the sinking of some current (about 1/2ÎIL).

Since the switching noise is constant in this mode, it is

also the easiest to ï¬lter out. In many cases, the output

voltage can be simply connected to the SYNC/MODE pin,

selecting the forced continuous mode except at start-up.

The LTC3417A-2 can be synchronized to an external clock

signal by the SYNC/MODE pin. The internal oscillator fre-

quency should be set to 20% lower than the external clock

frequency to ensure adequate slope compensation, since

slope compensation is derived from the internal oscillator.

During synchronization, the mode is set to pulse skipping

and the top switch turn-on is synchronized to the rising

edge of the external clock.

When using an external clock, with the PHASE pin low, the

switching of the two channels occur at the edges of the

external clock. A 50% duty cycle will therefore produce

180Â° out-of-phase operation.

Checking Transient Response

The ITH pin compensation allows the transient response

to be optimized for a wide range of loads and output

capacitors. The availability of the ITH pin not only allows

optimization of the control loop behavior, but also pro-

vides a DC coupled and AC ï¬lited closed-loop response

test point. The DC step, rise time, and settling at this test

point truly reï¬ects the closed-loop response. Assuming a

predominantly second order system, phase margin and/or

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also be

estimated using the percentage of overshoot seen at this

pin or by examining the rise time at this pin.

VRUN

2V/DIV

VOUT

1V/DIV

0.5A/DIV

VIN = 3.6V

VOUT = 2.5V

RL = 2Î©

200Î¼s/DIV

3417A-2 F03

Figure 3. Digital Soft-Start OUT2

3417a2fa

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