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LTC3331_15 Datasheet, PDF (13/34 Pages) Linear Technology – Nanopower Buck-Boost DC/DC with Energy Harvesting Battery Charger
LTC3331
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
Battery Connect/Disconnect
vs Temperature
4.4
4.0, 4.1, 4.2 FLOAT
4.2 LBSEL = 0
IBAT_OUT = 1mA
4.0
3.8
CONNECT, BAT_OUT
3.6
3.4
3.2
CONNECT, BAT_IN
3.0
2.8
DISCONNECT, BAT_OUT, BAT_IN
2.6
–50 –25
0 25 50 75 100 125
TEMPERATURE (°C)
3331 G58
Battery Connect/Disconnect
vs Temperature
4.4
CONNECT, BAT_OUT
4.2
4.0
Battery Connect Transient
BATTERY
DISCONNECTED
BAT_IN
3.8
3.6
CONNECT, BAT_IN
500mV/DIV VOUT
BAT_OUT
3.4
DISCONNECT, BAT_OUT, BAT_IN
3.2
3.0
4.0, 4.1, 4.2 FLOAT
2.8 LBSEL = 1
IBAT_OUT = 1mA
2.6
–50 –25 0 25 50 75
TEMPERATURE (°C)
100 125
0V
500ms/DIV
3331 G60
CBAT_IN = 1mF
CBB_IN = 22µF, BB_IN TIED TO BAT_OUT
1mA LOAD AT VOUT
FLOAT[1:0] = 11, LBSEL = 0
3331 G59
Supercapacitor Balancer
Quiescent Current vs VSCAP
250
125°C
200
85°C
150
25°C
100
–40°C
50
Supercapacitor Balancer
Source/Sink Current
50
40
SCAP = 5V
30
20
10
SCAP = 2.5V
0
–10
0
2 2.5 3 3.5 4 4.5 5 5.5
VSCAP (V)
3330 G61
–20
0
10 20 30 40 50 60 70 80 90 100
VBAL/VSCAP (%)
3330 G62
PIN FUNCTIONS
BAL (Pin 1): Supercapacitor Balance Point. The common
node of a stack of two supercapacitors is connected to
BAL. A source/sink balancing current of up to 10mA is
available. Tie BAL along with SCAP to GND to disable the
balancer and its associated quiescent current.
SCAP (Pin 2): Supply and Input for Supercapacitor
Balancer. Tie the top of a 2-capacitor stack to SCAP and
the middle of the stack to BAL to activate balancing. Tie
SCAP along with BAL to GND to disable the balancer and
its associated quiescent current.
VIN2 (Pin 3): Internal Low Voltage Rail to Serve as Gate
Drive for Buck NMOS Switch. Connect a 4.7µF (or larger)
capacitor from VIN2 to GND. This pin is not intended for
use as an external system rail.
UV3, UV2, UV1, UV0 (Pins 4, 5, 6, 7): UVLO Select Bits
for the Buck Switching Regulator. Tie high to VIN2 or low to
GND to select the desired UVLO rising and falling thresholds
(see Table 4). The UVLO falling threshold must be greater
than the selected VOUT regulation level. Do not float.
For more information www.linear.com/LTC3331
3331fb
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