LTC2226H_15 Datasheet, PDF (13/18 Pages) Linear Technology – 12-Bit, 25Msps 125C ADC in LQFP

LTC2226H
APPLICATIONS INFORMATION
Input Range
The input range can be set based on the application.
The 2V input range will provide the best signal-to-noise
performance while maintaining excellent SFDR. The 1V
input range will have better SFDR performance, but the
SNR will degrade by 3.8dB.
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A differential clock can also be used along
with a low-jitter CMOS converter before the CLK pin (see
Figure 8).
The noise performance of the LTC2226H can depend on the
clock signal quality as much as on the analog input. Any
noise present on the clock signal will result in additional
aperture jitter that will be RMS summed with the inherent
ADC aperture jitter.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2226H is 25Msps.
For the ADC to operate properly, the CLK signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 18.9ns for the ADC internal circuitry to have enough
settling time for proper operation.
An optional clock duty cycle stabilizer circuit can be used
if the input clock has a non 50% duty cycle. This circuit
uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
falling edge is generated by a phase-locked loop. The
input clock duty cycle can vary and the clock duty cycle
stabilizer will maintain a constant 50% internal duty cycle.
If the clock is turned off for a long period of time, the duty
cycle stabilizer circuit will require a hundred clock cycles
for the PLL to lock onto the input clock. To use the clock
duty cycle stabilizer, the MODE pin should be connected
to 1/3V_DD or 2/3V_DD using external resistors.
If the clock duty cycle stabilizer is used, a >1µs high pulse
should be applied to the SHDN pin once the power supplies
are stable at power up.
The lower limit of the LTC2226H sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
for the LTC2226H is 1Msps.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Digital Output Buffers
Table 1. Output Codes vs Input Voltage
A_IN+ – A_IN–
D11 – D0
(2V Range)
OF
(Offset Binary)
>+1.000000V
1
11 11 1111 1111
+0.999512V
0
11 11 1111 1111
+0.999024V
0
11 11 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
10 00 0000 0001
0
10 00 0000 0000
0
01 11 1111 1111
0
01 11 1111 1110
–0.999512V
0
0000 0000 0001
–1.000000V
0
0000 0000 0000
<–1.000000V
1
0000 0000 0000
D11 – D0
(2’s Complement)
0111 1111 1111
0111 1111 1111
0111 1111 1110
00 00 0000 0001
00 00 0000 0000
11 11 1111 1111
11 11 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OV_DD and OGND, isolated
from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50W to external
circuitry and may eliminate the need for external damping
resistors.
2226hfc
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