LTC2224 Datasheet, PDF (13/24 Pages) Linear Technology – 12-Bit, 135Msps ADC

LTC2224
APPLICATIO S I FOR ATIO
CONVERTER OPERATION
As shown in Figure 1, the LTC2224 is a CMOS pipelined
multistep converter. The converter has five pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later (see the Timing Diagram section).
For optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
analog inputs can be driven single-ended with slightly
worse harmonic distortion. The encode input is differen-
tial for improved common mode noise immunity. The
LTC2224 has two phases of operation, determined by the
state of the differential ENC⁺/ENC^– input pins. For brevity,
the text will refer to ENC⁺ greater than ENC^– as ENC high
and ENC⁺ less than ENC^– as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is re-
peated for the third and fourth stages, resulting in a fourth
stage residue that is sent to the fifth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2224
CMOS differential sample-and-hold. The analog inputs are
connected to the sampling capacitors (C_SAMPLE) through
NMOS transistors. The capacitors shown attached to each
input (C_PARASITIC) are the summation of all other capaci-
tance associated with each input.
LTC2224
V_DD
15Ω
A_IN+
V_DD
A_IN–
15Ω
V_DD
C_PARASITIC
1pF
C_PARASITIC
1pF
C_SAMPLE
1.6pF
C_SAMPLE
1.6pF
ENC⁺
1.6V
6k
ENC^–
6k
1.6V
2224 F02
Figure 2. Equivalent Input Circuit
2224fa
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