LTC1864_07 Datasheet, PDF (13/24 Pages) Linear Technology – μPower, 16-Bit, 250ksps 1- and 2-Channel ADCs in MSOP

LTC1864/LTC1865
APPLICATIONS INFORMATION
LTC1864 OPERATION
Operating Sequence
The LTC1864 conversion cycle begins with the rising edge
of CONV. After a period equal to t_CONV, the conversion is
finished. If CONV is left high after this time, the LTC1864
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1864 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely. See Figure 1.
Analog Inputs
The LTC1864 has a unipolar differential analog input. The
converter will measure the voltage between the “IN⁺”
and “IN^–” inputs. A zero code will occur when IN⁺ minus
IN^– equals zero. Full scale occurs when IN⁺ minus IN^–
equals V_REF minus 1LSB. See Figure 2. Both the “IN⁺” and
“IN^–” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN^–”
is grounded and V_REF is tied to V_CC, a rail-to-rail input
span will result on “IN⁺” as shown in Figure 3.
Reference Input
The voltage on the reference input of the LTC1864 defines
the full-scale range of the A/D converter. The LTC1864 can
operate with reference voltages from V_CC to 1V.
CONV
SCK
SDO
t_CONV
SLEEP MODE
t_suCONV
t_SMPL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
Hi-Z
Hi-Z
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
18645 F01
Figure 1. LTC1864 Operating Sequence
1111111111111111
1111111111111110
•
•
•
0000000000000001
0000000000000000
*V_IN = IN⁺ – IN^–
Figure 2. LTC1864 Transfer Curve
V_IN*
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1μF
V_CC
LTC1864
1
V_REF
V_IN = 0V TO V_CC ² IN⁺
3 _IN–
8
V_CC
7
SCK
6
SDO
4
GND
5
CONV
18645 F03
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
Figure 3. LTC1864 with Rail-to-Rail Input Span
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