LTC1412 Datasheet, PDF (13/16 Pages) Linear Technology – 12-Bit, 3Msps, Sampling A/D Converter

LTC1412
APPLICATIONS INFORMATION
– 5V
R1
50k
R3
24k
ANALOG INPUT ¹ A_IN+
R4
100Ω
2 _AIN–
R5 R2
47k 50k
R6
24k
LTC1412
3
V_REF
4
REFCOMP
10µF
5
AGND
1412 F11b
Figure 11b. Offset and Full-Scale Adjust Circuit
– 0.61mV (i.e., – 0.5LSB) at A_IN+ and adjust the offset at
the A_IN– input until the output code flickers between 0000
0000 0000 and 1111 1111 1111. For full-scale adjust-
ment, an input voltage of 2.49817V (FS/2 – 1.5LSBs) is
applied to A_IN+ and R2 is adjusted until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
Board Layout and Bypassing
To obtain the best performance from the LTC1412, a
printed circuit board with ground plane is required. Layout
for the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital line
alongside an analog signal line.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pins 22 and 14 (DGND) and Pin 19 (OGND)
and all other analog grounds should be connected to this
single analog ground point. The REFCOMP bypass capaci-
tor and the DV_DD bypass capacitor should also be con-
nected to this analog ground plane, see Figure 12. All
analog circuitry grounds should be terminated to this
analog ground plane. The ground return from the ground
plane to the power supply should be low impedance.
Digital circuitry grounds must be connected to the digital
supply common. Low impedance analog and digital power
supply lines are essential to low noise operation of the
ADC. The traces connecting the pins and bypass capaci-
tors must be kept short and should be made as wide as
possible.
The LTC1412 has differential inputs to minimize noise
coupling. Common mode noise on the A_IN+ and A_IN– leads
will be rejected by the input CMRR. The A_IN– input can be
used as a ground sense for the A_IN+ input; the LTC1412
will hold and convert the difference voltage between A_IN+
and A_IN–. The leads to A_IN+ (Pin 1) and A_IN– (Pin 2) should
be kept as short as possible. In applications where this is
not possible, the A_IN+ and A_IN– traces should be run side
by side to equalize coupling.
Supply Bypassing
High quality, low series resistance ceramic, 10µF bypass
capacitors should be used at the V_DD and REFCOMP pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively 10µF tantalum capacitors
in parallel with 0.1µF ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
Example Layout
Figures 13a, 13b, 13c and 13d show the schematic and
layout of an evaluation board. The layout demonstrates the
proper use of decoupling capacitors and ground plane
with a two layer printed circuit board.
1 _AIN+
A_{IN– REFCOMP AGND}
ANALOG
INPUT
+–
CIRCUITRY
2
+
10µF
4
5₊
0.1µF
LTC1412
V_SS
26
+
10µF
0.1µF
AV_DD OV_DD DV_DD DGND OGND
28 20 21, 27 14, 22 19
10µF
0.1µF
DIGITAL
SYSTEM
ANALOG GROUND PLANE
Figure 12. Power Supply Grounding Practice
1412 F12
POWER
SUPPLY
GROUND
13