LTC1400_1 Datasheet, PDF (13/20 Pages) Linear Technology – Complete SO-8, 12-Bit, 400ksps ADC with Shutdown

LTC1400
APPLICATIO S I FOR ATIO
In the Sleep mode, power consumption is reduced to a
minimum by cutting off the supply to all internal circuitry
including the reference. Figure 12 shows the ways to power
down the LTC1400. The chip can enter the Nap mode by
keeping the CLK signal low and pulsing the CONV signal
twice. For Sleep mode operation, CONV signal should be
pulsed four times while CLK is kept low.
The LTC1400 can be returned to active mode easily. The
rising edge of CLK will wake-up the LTC1400. During the
transition from Sleep mode to active mode, the V_REF volt-
age ramp-up time is a function of the loading conditions.
With a 10μF bypass capacitor, the wake-up time from
Sleep mode is typically 4ms. A REFRDY signal will be
activated once the reference has settled and is ready for
an A/D conversion. This REFRDY bit is output to the D_OUT
pin before the rest of the A/D converted code.
Digital Interface
The digital interface requires only three digital lines. CLK
and CONV are both inputs, and the D_OUT output provides
the conversion result in serial form.
Figure 13 shows the digital timing diagram of the LTC1400
during the A/D conversion. The CONV rising edge starts
the conversion. Once initiated, it can not be restarted until
the conversion is completed. If the time from CONV signal
to CLK rising edge is less than t₂, the digital output will
be delayed by one clock cycle.
The digital output data is updated on the rising edge of the
CLK line. D_OUT data should be captured by the receiving
system on the rising CLK edge. Data remains valid for a
minimum time of t₁₀ after the rising CLK edge to allow
capture to occur.
CLK
CONV
INTERNAL
S/H STATUS
SAMPLE
D_OUT
t₂
t₃
t₇
1
2
34
5
6
7
8
9 10 11 12 13 14 15 1
2
t₄
t₅
t₆
HOLD
t_ACQ
SAMPLE
t₈
Hi-Z _{REFRDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0}
HOLD
Hi-Z _REFRDY
t_CONV
t_SAMPLE
1400 F13
Figure 13. ADC Digital Timing Diagram
CLK
V_IH
CLK
V_IH
D_OUT
t₈
t ₁₀
t₉
V_OH
D_OUT
V_OL
Figure 14. CLK to D_OUT Delay
90%
10%
1400 F14
1400fa
13