LTC1298_15 Datasheet, PDF (13/24 Pages) Linear Technology – Micropower Sampling 12-Bit A/D Converters In S0-8 Packages

APPLICATION INFORMATION
CS
MSBF BIT LATCHED
BY LTC1298
1
2
3
4
CLK
LTC1286/LTC1298
DATA (D_IN/D_OUT)
START
SGL/DIFF
ODD/SIGN
MSBF
B11
B10
•••
MPU CONTROLS DATA LINE AND SENDS
MUX ADDRESS TO LTC1298
PROCESSOR MUST RELEASE
DATA LINE AFTER 4TH RISING CLK
AND BEFORE THE 4TH FALLING CLK
LTC1298 CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO MPU
LTC1298 TAKES CONTROL OF DATA LINE
ON 4TH FALLING CLK
LTC1286/98 F03
Figure 3. LTC1298 Operation with D_IN and D_OUT Tied Together
ACHIEVING MICROPOWER PERFORMANCE
With typical operating currents of 250µA and automatic
shutdown between conversions, the LTC1286/LTC1298
achieves extremely low power consumption over a wide
range of sample rates (see Figure 4). The auto-shutdown
allows the supply curve to drop with reduced sample rate.
Several things must be taken into account to achieve such
a low power consumption.
1000
T_A = 25°C
V_CC = V_REF = 5V
f_CLK = 200kHz
100
LTC1298
LTC1286
10
1
0.1k
1k
10k
SAMPLE RATE (kHz)
100k
LT1286/98 G03
Figure 4. Automatic Power Shutdown Between Conversions
Allows Power Consumption to Drop with Sample Rate.
Shutdown
The LTC1286/LTC1298 are equipped with automatic shut-
down features. They draw power when the CS pin is low
and shut down completely when that pin is high. The bias
circuit and comparator powers down and the reference
input becomes high impedance at the end of each conver-
sion leaving the CLK running to clock out the LSB first data
or zeroes (see Figures 1 and 2). If the CS is not running rail-
to-rail, the input logic buffer will draw current. This current
may be large compared to the typical supply current. To
obtain the lowest supply current, bring the CS pin to
ground when it is low and to supply voltage when it is high.
When the CS pin is high (= supply voltage), the converter
is in shutdown mode and draws only leakage current. The
status of the D_IN and CLK input have no effect on supply
current during this time. There is no need to stop D_IN and
CLK with CS = high; they can continue to run without
drawing current.
Minimize CS Low Time
In systems that have significant time between conver-
sions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transferring data as quickly as
possible, and then bringing it back high will result in the
lowest current drain. This minimizes the amount of time
the device draws power. After a conversion the ADC
automatically shuts down even if CS is held low (see
Figures 1 and 2). If the clock is left running to clock out
LSB-data or zero, the logic will draw a small current.
Figure 5 shows that the typical supply current with CS =
ground varies from 1µA at 1kHz to 35µA at 200kHz. When
CS = V_CC, the logic is gated off and no supply current is
drawn regardless of the clock frequency.
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