LTC1293 Datasheet, PDF (13/28 Pages) Linear Technology – Single Chip 12-Bit Data Acquisition System

LTC1293/LTC1294/LTC1296
APPLICATI S I FOR ATIO
Example 2: The same conditions as Example 1 except
COM = 1V. The resulting input span is 1V ≤ IN⁺ ≤ 4V. Note
if IN⁺ ≥ 4V the resulting D_OUT word is all 1’s. If IN⁺ ≤ 1V
then the resulting D_OUT word is all 0’s.
Example 3: Let V_CC = 5V, V ^– = –5V, REF⁺ = 4V, REF^– = 1V
and COM = 1V. Bipolar mode of operation. The resulting
input span is –2V ≤ IN⁺ ≤ 4V.
For differential input configurations with the same condi-
tions as in the above three examples the resulting input
spans are as follows:
Example 1 (Diff.): IN^– ≤ IN⁺ ≤ IN^– + 3V.
Example 2 (Diff.): IN^– ≤ IN⁺ ≤ IN^– + 3V.
Example 3 (Diff.): IN^– – 3V ≤ IN⁺ ≤ IN^– + 3V.
MSB-First/LSB-First (MSBF)
The output data of the LTC1293/4/6 is programmed for
MSB-first or LSB-first sequence using the MSB bit. When
the MSBF bit is a logical one, data will appear on the D_OUT
line in MSB-first format. Logical zeroes will be filled in
indefinitely following the last data bit to accommodate
longer word lengths required by some microprocessors.
When the MSBF bit is a logical zero, LSB first data will
follow the normal MSB first data on the D_OUT line. In the
bipolar mode the sign bit will fill in after the MSB bit for
MSBF = 0 (see Operating Sequence).
Power Shutdowns (PS)
The power shutdown feature of the LTC1293/4/6 is acti-
vated by making the PS bit a logical zero. If CS remains low
after the PS bit has been received, a 12-bit D_OUT word with
Operating Sequence
Example: Differential Inputs (CH4⁺, CH5^–), Unipolar Mode
MSB-FIRST DATA (MSBF = 1)
t_CYC
CS
CLK
D_IN
D_OUT
START
SEL1 UNI PS
MSBF
SGL/ ODD/ SEL0
DIFF SIGN
B11
HI-Z
t_SMPL
MSB-FIRST DATA (MSBF = 0)
CS
t_CONV
DON'T CARE
B1 B0
FILLED WITH ZEROES
t_CYC
DON'T
CARE
CLK
D_IN
D_OUT
START
SEL1 UNI PS
SGL/ ODD/ SEL0 MSBF
DIFF SIGN
B11
HI-Z
t_SMPL
t_CONV
DON'T CARE
B1 B0 B1
DON'T
CARE
B11
FILLED WITH
ZEROES
LTC1293 AI05
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