LT3582_15 Datasheet, PDF (13/28 Pages) Linear Technology – Boost and Single Inductor Inverting DC/DC Converters with Optional I2C Programing and OTP

LT3582/LT3582-5/LT3582-12
APPLICATIONS INFORMATION
CMDR: The Command Register is used to control various
functions of the chip. During shutdown and power-up the
CMDR is initialized to 00h.
The RSEL (Register Select) bits are functional only for
the LT3582. The LT3582-5 and LT3582-12 function as if
the RSEL bits are always “0”. These bits perform three
functions:
• Each RSEL bit instructs the chip whether to use the
configuration data from the corresponding OTP byte
(RSELx = 0) or the REG byte (RSELx = 1). Changing an
RSELx bit immediately updates the chip configuration.
• Each RSEL bit determines if I²C reads return data from
the corresponding OTP byte (RSELx = 0) or the REG
byte (RSELx = 1).
• OTP programming only programs data to the bytes with
corresponding RSEL bits set high.
Setting the SWOFF bit immediately disables the Boost
and Inverting power switches and opens the output dis-
connect PMOS switch. It is recommended to set this bit
before writing new configuration data. This can prevent
unexpected chip behavior while modifying the configura-
tion and also forces a soft-start after SWOFF is cleared
(see Soft-Start and Power-Up Sequencing). Writing “1”
to the RST bit resets the internal I²C logic and the CMDR
register. Reading bit 6 of the CMDR returns the FAULT bit
indicating if an OTP programming attempt may have failed.
FAULT is cleared during reset, power-up, or by writing a “1”
to the CF (Clear Fault) bit. Conditions that set the FAULT
bit are (1) OTP programming in which the V_PP voltage
is too low or (2) attempted OTP programming when the
LOCK bit is set. OTP write attempts that set the FAULT bit
due to low V_PP voltage should be considered failures and
the device should be discarded. Attempts to re-program
the OTP memory after the FAULT bit has been set are not
recommended. Finally, setting the WOTP bit starts the
OTP programming.
Table 1: LT3582 Series Register Map
REGISTER REGIS- BIT BIT DESCRIPTION
ADDRESS TER
NAME
NAME
00h REG0/ 7:0 V_P V_OUTP Output Voltage (00h=3.2V,
OTP0
BFh = 12.75V)
01h REG1/ 7:0 V_N V_OUTN Output Voltage (00h=1.2V,
OTP1
FFh = 13.95V)
7 - Reserved, Write to 0
6 LOCK Lockout Bit: See the OTP
Programming Lockout Section.
02h
REG2/ 5 V_PLUS V_OUTP Output Voltage Bit: Increase
OTP2
V_OUTP by ~25mV
4:3 IRMP RAMPP and RAMPN Pull-Up
Current: I_RAMP = (2) ^IRMP μA
2 PDDIS Power-Down Discharge Enable.
PUSEQ Must be 11 if Set.
1:0 PUSEQ Power-Up Sequencing: 00 =
Outputs Disabled, 01 = V_OUTN
Ramp 1st, 10 = V_OUTP Ramp 1st,
11 = Both Ramp Together
7 WOTP Write OTP Memory
6 CF/ Clear Fault/OTP Programming
FAULT Fault
5 RST Reset
4 SWOFF Switches-Off
04h CMDR 3 - Reserved, Write to 0
2 RSEL2 Register Select 2 (0 = OTP2,
1 = REG2)
1 RSEL1 Register Select 1 (0 = OTP1,
1 = REG1)
0 RSEL0 Register Select 0 (0 = OTP0,
1 = REG0)
OTP0/REG0 and OTP1/REG1: Data in addresses 00h and
01h is used to set the output voltages of the Boost and
Inverting converters respectively. See Setting the Output
Voltages for more information.
3582512fb
13