LT1016_03 Datasheet, PDF (13/20 Pages) Linear Technology – UltraFast Precision 10ns Comparator

LT1016
APPLICATIO S I FOR ATIO
1.8ms, 12-Bit A/D Converter
The LT1016’s high speed is used to implement a very fast
12-bit A/D converter in Figure 15. The circuit is a modified
form of the standard successive approximation approach
and is faster than most commercial SAR 12-bit units. In
this arrangement the 2504 successive approximation reg-
ister (SAR), A1 and C1 test each bit, beginning with the
MSB, and produce a digital word representing V_IN’s value.
To get faster conversion time, the clock is controlled by the
window comparator monitoring the DAC input summing
junction. Additionally, the DMOS FET clamps the DAC
output to ground at the beginning of each clock cycle,
shortening DAC settling time. After the fifth bit is con-
verted, the clock runs at maximum speed.
5V
0.01µF
2.5k
5V
– 5V
1k
1000pF
SD210
5V ^{LT1021 10V}
10V
10k** 10k
14
V_R+
0.01µF
–15V
16
COMP
15
V_R–
13
19
GND
I_O
AM6012
15V
20
V⁺
–15V
17
V^–
I_O ¹⁸
150Ω 620Ω*
V_IN
0V TO 10V
620Ω*
– 5V
–
C1
2.5k**
Q3
LT1016
+
NC
1k
1k
5V
150k
Q1 Q2
5V
9
6
74121 Q
IN B
345 7
PARALLEL
DIGITAL MSB
DATA
OUTPUT _5V ²⁴ _V+
13
CLK
Q6
AM2504
GND
E
12
1
S
CC
14
3
LSB
11
D
150k
15k
Q4
27k
–15V
Q5
1/4 74S00
Q1 TO Q5 RCA CA3127 ARRAY
1N4148
HP5082-2810
*1% FILM RESISTOR
**PRECISION 0.01%; VISHAY S-102
5V
1k
0.1µF 10Ω
5V
–
C3
LT1016
+
– 5V
1k
0.1µF _10Ω
– 5V
5V
+
C2
LT1016
–
– 5V
NC
1/4 74S08
1/4 74S00
PRS
D
Q
1/2 74S74
CLK
PRS
1/4 74S08
1/2 74S74
NC
RST
1/6 74S04 1/6 74S04
CLOCK
7.4MHz
Figure 15. 12-Bit 1.8ms SAR A-to-D
STATUS
CONVERT
COMMAND
1016 F15
13