LTC4252-2_15 Datasheet, PDF (12/36 Pages) Linear Technology – Negative Voltage Hot Swap Controllers

LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
Operation
Hot Circuit Insertion
Interlock Conditions
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient currents
from the power bus as they charge. The flow of current
damages the connector pins and glitches the power bus,
causing other boards in the system to reset. The LTC4252
is designed to turn on a circuit board supply in a controlled
manner, allowing insertion or removal without glitches or
connector damage.
Initial Start-Up
The LTC4252 resides on a removable circuit board and
controls the path between the connector and load or power
conversion circuitry with an external MOSFET switch (see
Figure 1). Both inrush control and short-circuit protection
are provided by the MOSFET.
A detailed schematic for the LTC4252A is shown in Figure 2.
– 48V and –48RTN receive power through the longest con-
nector pins and are the first to connect when the board is
inserted. The GATE pin holds the MOSFET off during this
time. UV and OV determine whether or not the MOSFET
should be turned on based upon internal high accuracy
thresholds and an external divider. UV and OV do double
duty by also monitoring whether or not the connector is
seated. The top of the divider detects –48RTN by way of
a short connector pin that is the last to mate during the
insertion sequence.
LONG
– 48RTN
LONG
– 48V
BACKPLANE
PLUG-IN BOARD
LTC4252 +
C_LOAD
+
+
ISOLATED
DC/DC
CONVERTER
MODULE
–
–
LOW
VOLTAGE
CIRCUITRY
4252-1/2 F01
Figure 1. Basic LTC4252 Hot Swap Topology
A start-up sequence commences once these “interlock”
conditions are met.
1. The input voltage V_IN exceeds V_LKO (UVLO).
2. The voltage at UV > V_UVHI.
3. The voltage at OV < V_OVLO.
4. The (SENSE – V_EE) voltage is < 50mV (V_CB).
5. The voltage at SS is < 0.2V (20 • V_OS).
6. The voltage on the TIMER capacitor (C_T) is < 1V (V_TMRL).
7. The voltage at GATE is < 0.5V (V_GATEL).
The first three conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
TIMER begins the start-up sequence by sourcing 5.8µA
into C_T. If V_IN, UV or OV falls out of range, the start-up
cycle stops and TIMER discharges C_T to less than 1V, then
waits until the aforementioned conditions are once again
met. If C_T successfully charges to 4V, TIMER pulls low
and both SS and GATE pins are released. GATE sources
58µA (I_GATE), charging the MOSFET gate and associated
capacitance. The SS voltage ramp limits V_SENSE to control
the inrush current. PWRGD pulls active low when GATE is
within 2.8V of V_IN and DRAIN is lower than V_DRNL.
LONG
– 48RTN
D_IN+
DDZ13B**
R_IN
3 × 1.8k IN SERIES
1/4W EACH
C_LOAD ⁺
100µF
SHORT ^R1
392k
1%
C1
10nF
C_IN
1µF
OV
V_IN
UV
LTC4252A-1
TIMER
SS
DRAIN
C_SS ^{VEE SENSE GATE}
R2
68nF
30.1k
1%
C_T
0.68µF
C_C
R_C
10Ω
10nF
LONG
– 48V
R_S
Q1
**DIODES, INC
0.02Ω _IRF530S
†_{RECOMMENDED FOR HARSH ENVIRONMENTS}
R_D
1M
425212 F02
Figure 2.­–48V, 2.5A Hot Swap Controller
425212fe
12
For more information www.linear.com/LTC4252-1