LTC3705_15 Datasheet, PDF (12/20 Pages) Linear Technology – 2-Switch Forward Controller and Gate Driver

LTC3705
APPLICATIO S I FOR ATIO
In the event that a short-circuit is applied to the output of
the converter prior to start-up, the LTC3706 generally
does not receive enough bias voltage to operate. In this
case, the LTC3705 detects a FAULT for one of two reasons:
1) since the LTC3706 never sends pulse encoding to the
LTC3705, the linear regulator times out resulting in a gate
drive undervoltage fault, or 2) the primary-side overcurrent
circuit is tripped because of current buildup in the output
inductor. In either case, the LTC3705 initiates a shutdown
followed by a soft-start retry.
Linear Regulator Timeout
After start-up, the LTC3705 times out the linear regulator
to prevent overheating of the external NMOS. The timeout
interval is set by further charging the soft-start capacitor
C_SSFLT from the end-of-soft-start voltage of approximately
2.8V to the timeout threshold of 3.9V. Linear regulator
timeout behaves differently depending on mode.
In primary-side standalone mode, the LTC3705 generally
requires that an auxiliary gate drive bias supply take over
from the linear regulator. (See the subsequent section for
more detail on the auxiliary supply.) During linear regula-
tor timeout, the rate of rise of the soft-start capacitor
voltage depends on the current into the NDRV pin as
controlled by the pull-up resistor R_PULLUP, the value of V_IN
and the value of V_NDRV.
I_NDRV
=
V_IN – V_NDRV
R_PULLUP
The value of V_NDRV is V_CC = 8V plus the value of the gate-
to-source voltage (V_NDRV – V_CC) of the external NMOS in
the linear regulator. The gate-to-source voltage depends
on the actual device but is approximately the threshold
voltage of the external NMOS.
For I_NDRV > 0.27mA, the capacitor on the SSFLT pin is
charged in proportion to (I_NDRV – 0.27mA) until the linear
regulator times out. Thus, since V_NDRV is very nearly
constant, the timeout interval for the linear regulator is
inversely proportional to the input voltage and a higher
input voltage produces a shorter timeout.
t_TIMEOUT
=
66C_SSFLT (3.9V – 2.8V)
⎡V_IN − V_NDRV
⎣⎢ ^RPULLUP
–
0.27mA^{⎤⎦⎥}
12
Since the power dissipation of the linear regulator is
proportional to the input voltage, this strategy of making
the timeout inversely proportional to the input voltage
produces an approximately constant temperature excur-
sion for the external NMOS of the linear regulator regard-
less of the input voltage.
In situations for which the continuous operation of the
linear regulator does not exceed the thermal limitations of
the external NMOS (i.e. converters with low V_IN or with
minimal gate drive bias requirements), the auxiliary sup-
ply can be omitted and the linear regulator allowed to
operate continuously. If I_NDRV is less than 0.27mA the
linear regulator never times out and the voltage on the
SSFLT pin stays at approximately 2.8V after start-up is
completed. To accomplish this set:
R_PULLUP
>
V_IN(MAX) – V_NDRV
0.27mA
where V_IN(MAX) is the maximum expected continuous
input voltage. Note that once the linear regulator is turned
off it locks out. Therefore when using this strategy, care
should be taken to ensure that a transient higher than
V_IN(MAX) does not persist longer than t_TIMEOUT.
In secondary-side operation with the LTC3706, there is
never any need for continuous operation of the linear
regulator since gate drive bias power is provided by the
LTC3706 through the pulse transformer and on-chip
rectifier. The LTC3705 shuts down the linear regulator
once the LTC3706 begins switching the pulse trans-
former. If the LTC3706 fails to start, the LTC3705 quickly
times out the linear regulator once the voltage on the
SSFLT pin reaches 2.8V.
Fault Lockout
The LTC3705 indicates a fault by pulling the SSFLT pin to
within 1V of V_CC. The LTC3705 subsequently attempts a
restart. Optionally, the user can prevent restart and “lock
out” the converter by clamping the voltage on the SSFLT
pin with a 4.3V Zener diode. Once the converter has locked
out it can only be restarted by the removal of the input
voltage or by release of the Zener diode clamp.
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