LTC2668_15 Datasheet, PDF (12/28 Pages) Linear Technology – 16-Channel 16-/12-Bit 10V VOUT SoftSpan DACs with 10ppm/C Max Reference

LTC2668
Pin Functions
MSP2 (Pin 1): MSPAN Bit 2. Tie this pin to AVP or GND
to select the power-on span and power-on-reset code for
all 16 channels (see Table 4).
V_OUT0 to V_OUT15 (Pins 2-9, 23-30): DAC Analog Voltage
Outputs.
V⁺ (Pins 10, 31): Analog Positive Supply. Typically 15V;
4.5V to 15.75V range. Bypass to GND with a 1µF capacitor.
V^– (Pins 11, 32, 41): Analog Negative Supply. Typically
–15V; –4.5V to –15.75V range, or can be tied to GND.
Bypass to GND with a 1µF capacitor unless V^– is con-
nected to GND.
MUX (Pin 12): Analog Multiplexer Output. Any of the 16
DAC outputs can be internally routed to the MUX pin. When
the mux is disabled, this pin becomes high impedance.
REFLO (Pins 13, 35): Reference Low Pins. Signal ground
for all DAC channels and internal reference. These pins
should be tied to GND.
GND (Pins 14, 37): Analog Ground. Tie to a clean analog
ground plane.
LDAC (Pin 15): Active-low Asynchronous DAC Update
Pin. If CS/LD is high, a falling edge on LDAC immediately
updates all DAC registers with the contents of the input
registers (similar to a software update). If CS/LD is low
when LDAC goes low, the DAC registers are updated after
CS/LD returns high. A low on the LDAC pin powers up
the DACs. A software power-down command is ignored if
LDAC is low. Logic levels are determined by OVP.
Tie LDAC high (to OVP) if not used. Updates can then be
performed through SPI commands (see Table 1).
CS/LD (Pin 16): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When CS/LD is taken high, SCK
is disabled and the specified command (see Table 1) is
executed. Logic levels are determined by OVP.
SCK (Pin 17): Serial Interface Clock Input. Logic levels
are determined by OVP.
SDO (Pin 18): Serial Interface Data Output. The serial
output of the 32-bit shift register appears at the SDO
pin. The data transferred to the device via the SDI pin is
delayed 32 SCK rising edges before being output at the
next falling edge. Can be used for data echo readback or
daisy-chain operation (pull-up/down resistor required).
The SDO pin becomes high impedance when CS/LD is
high. Logic levels are determined by OVP.
SDI (Pin 19): Serial Interface Data Input. Data on SDI
is clocked into the DAC on the rising edge of SCK.
The LTC2668 accepts input word lengths of either 24 or
32 bits. Logic levels are determined by OVP.
TGP (Pin 20): Asynchronous Toggle Pin. A falling edge
updates the DAC register with data from input register A.
A rising edge updates the DAC register with data from
input register B. Toggle operations only affect those DAC
channels with their toggle select bit (Tx) set to 1. Tie the
TGP pin to OVP if toggle operations are to be done through
software. Tie the TGP pin to GND if not using toggle opera-
tions. Logic levels are determined by OVP.
CLR (Pin 21): Active-low Asynchronous Clear Input. A
logic low at this level-triggered input clears the part to the
reset code and range determined by the hardwired option
chosen using the MSPAN pins and specified in Table 4.
The control registers are cleared to zero. Logic levels are
determined by OVP.
OVP (Pin 22): Digital Input/Output Supply Voltage. 1.71V ≤
OVP ≤ AVP + 0.3V. Bypass to GND with a 0.1µF capacitor.
REF (Pin 33): Reference In/Out. The voltage at the REF
pin sets the full-scale range of all channels. By default, the
internal reference is routed to this pin. Must be buffered
when driving external DC load currents. If the reference
is disabled (see Reference Modes in the Operation
section), its output is disconnected and the REF pin
becomes a high impedance input to which you may
apply a precision external reference. For low noise and
reference stability, tie a capacitor from this pin to GND.
The value must be ≤ C_REFCOMP, where C_REFCOMP is
the capacitance tied to the REFCOMP pin. The allow-
able external reference input voltage range is 0.5V to
V_AVP – 1.75V.
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