LTC2483_15 Datasheet, PDF (12/34 Pages) Linear Technology – 16-Bit ADC with Easy Drive Input Current Cancellation and I2C Interface

LTC2483
Applications Information
The START and STOP Conditions
A START condition is generated by transitioning SDA from
HIGH to LOW while SCL is HIGH. The bus is considered to
be busy after the START condition. When the data transfer
is finished, a STOP condition is generated by transitioning
SDA from LOW to HIGH while SCL is HIGH. The bus is free
again a certain time after the STOP condition. START and
STOP conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The re-
peated START (Sr) conditions are functionally identical
to the START (S).
Data Transferring
After the START condition, the I²C bus is busy and data
transfer is set between a master and a slave. Data is
transferred over I²C in groups of nine bits (one byte)
followed by an acknowledge bit, therefore each group
takes nine SCL cycles. The transmitter releases the SDA
line during the acknowledge clock pulse and the receiver
issues an acknowledge (ACK) by pulling SDA LOW or
leaves SDA HIGH to indicate a Not Acknowledge (NACK)
condition. Change of data state can only happen while
SCL is LOW.
SDA
t_f
SCL
S
t_LOW
t_r
t_SU;DAT
t_r
t_HD;STA
t_SP
t_r
t_BUF
t_HD;STA
t_HD;DAT
t_HIGH
t_SU;STA
Sr
t_SU;STO
P
Figure 2. Definition of Timing for F/S Mode Devices on the I²C Bus
S
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