LTC2247_15 Datasheet, PDF (12/24 Pages) Linear Technology – 14-Bit, 65/40/25Msps Low Power 3V ADCs

LTC2248/LTC2247/LTC2246
W
FUNCTIONAL BLOCK DIAGRA
A_IN+
INPUT
A_IN–
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
V_CM
2.2µF
1.5V
REFERENCE
RANGE
SELECT
REF
SENSE
BUF
REFH
REFL INTERNAL CLOCK SIGNALS
DIFF
CLOCK/DUTY
CONTROL
REF
CYCLE
LOGIC
AMP
CONTROL
SHIFT REGISTER
AND CORRECTION
OUTPUT
DRIVERS
OV_DD
OF
D13
•
•
•
D0
REFH 0.1µF REFL
2.2µF
1µF
1µF
CLK
M0DE SHDN
OE
OGND
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Figure 1. Functional Block Diagram
WU
W
TI I G DIAGRA
Timing Diagram
ANALOG
INPUT
CLK
D0-D13, OF
t_AP
N
t_H
N+1
t_L
N+2
N+3
N+4
t_D
N–5
N–4
N–3
N–2
N+5
N–1
N
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