LTC1695_15 Datasheet, PDF (12/20 Pages) Linear Technology – SMBus/IC Fan Speed Controller in SOT-23

LTC1695
APPLICATIONS INFORMATION
SMBus SEND BYTE PROTOCOL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
S 1 1 1 0 1 0 0 0 0 X BST D5 D4 D3 D2 D1 D0 0 P
A6 A5 A4 A3 A2 A1 A0 W A
START
SLAVE ADDRESS
MSB
COMMAND BYTE
LSB A
STOP
SMBus RECEIVE BYTE PROTOCOL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
S 1 1 1 0 1 0 0 1 0 OCF THE 0 0 0 0 0 0 1 P
A6 A5 A4 A3 A2 A1 A0 W A
START
SLAVE ADDRESS
DATA BYTE
A
STOP
S = SMBus START BIT
P = SMBus STOP BIT
BST = 1 ENABLES THE BOOST START TIMER
D5 TO D0 = 6-BIT INPUT CODE FOR THE DAC (D5 = MSB)
OCF = 1 SIGNALS THAT THE LTC1695 IS IN CURRENT LIMIT
THE = 1 SIGNALS THAT THE LTC1695 IS IN THERMAL SHUTDOWN
BIT 18 = 1 IS A NOT ACKNOWLEDGE FOR RECEIVE BYTE PROTOCOL
NOTE: DURING POWER UP AND UVLO, DAC INPUT BITS
(D5 TO D0) AND THE BST BIT ARE RESET TO ZERO
1695 • F02
Figure 2. SMBus Interface Bit Definition
SCL and SDA
SCL is the synchronizing clock signal generated by the
host. SDA is the bidirectional data transfer line between
the host and a slave device. The host initiates a start bit by
pulling SDA from high to low while SCL is high. The stop
bit is initiated by changing SDA from low to high while SCL
is high. All address, command and acknowledge signals
must be valid and should not change while SCL is high.
The acknowledge bit signals to the host the acceptance of
a correct address byte or command byte.
The SCL and SDA input threshold voltages are typically
1.4V with 40mV of hysteresis. Connect the SCL and SDA
open-drain lines to either a resistive or current source pull
up. The LTC1695 SDA has an open-drain N-channel tran-
sistor capable of sinking 3mA at less than 0.4V during the
slave acknowledge sequence.
The LTC1695 is compatible with the Philips/Signetics I²C
Bus Interface. The 1.4V threshold for SCL and SDA does
not create any I²C application problems.
Early Stop Conditions
If a stop condition occurs before the data byte is acknowl-
edged in the write byte protocol, the LTC1695’s DAC is not
updated. Otherwise, the internal register is updated with
the new data and V_OUT changes accordingly to the new
programmed value.
Address, Command, Data Selection
The LTC1695’s address is hard-wired internally as 1110100
(MSB to LSB, A6 to A0). Consult LTC for parts with
alternate address codes. Consult the Address, Command
and Data Byte Tables for further information and as a
concise reference.
As shown in Figure 2, D5 to D0 in the command code,
control the linear regulator’s output voltage and thus fan
speed. D5 to D0 are sent from the host to the LTC1695
during send byte protocol. The LTC1695 latches D5 to D0
as DAC input data at the falling edge of the data acknowl-
edge signal. The host must set “BST” (boost start enable
bit) to high if the LTC1695’s 250ms boost start timer
option is used. All bits are reset to zero during power-on
reset and UVLO. As shown in the Timing Diagram, bit 6
and bit 7 in the data byte register are defined as thermal
shutdown status (THE) and over current fault (OCF) status
respectively. The LTC1695 sets OCF high if I_LOAD exceeds
390mA typically and “THE” high if junction temperature
exceeds 155°C typically. The remaining bits of the data
byte’s register (bit 5 to 0) are set low during host read
back.
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