LT1076_15 Datasheet, PDF (12/16 Pages) Linear Technology – Step-Down Switching Regulator

LT1074/LT1076
PI DESCRIPTIO S
90 µ A
50 µ A
Q3
D1
Q1
Q2
X1.8
FB _{50 µA}
D2
2.21V
140µ A
300 Ω
5.8V
Q4
90 µ A
V_C
90 µ A
EXTERNAL
FREQUENCY
COMPENSATION
R_C
Q6
C_C
ALL CURRENTS SHOWN ARE AT NULL CONDITION
Figure 10. Error Amplifier
LT1074 • PD11
A_V
=
2π
G_m
• f •C_C
at
mid
frequencies
A_V = G_m • R_C at high frequencies
Phase shift from the FB pin to the V_C pin is 90° at mid
frequencies where the external C_C is controlling gain, then
drops back to 0° (actually 180° since FB is an inverting
input) when the reactance of C_C is small compared to R_C.
The low frequency “pole” where the reactance of C_C is
equal to the output impedance of Q4 and Q6 (r_O), is:
f_POLE
=
2π
•
1
r_O
•
C
r_O
≈
400kΩ
Although f_POLE varies as much as 3:1 due to r_O variations,
mid-frequency gain is dependent only on G_m, which is
specified much tighter on the data sheet. The higher
frequency “zero” is determined solely by R_C and C_C.
f_ZERO
=
2π
1
• R_C
•
C_C
The error amplifier has asymmetrical peak output current.
Q3 and Q4 current mirrors are unity-gain, but the Q6
mirror has a gain of 1.8 at output null and a gain of 8 when
the FB pin is high (Q1 current = 0). This results in a
maximum positive output current of 140µA and a maxi-
mum negative (sink) output current of ≅1.1mA. The asym-
metry is deliberate—it results in much less regulator
output overshoot during rapid start-up or following the
release of an output overload. Amplifier offset is kept low
by area scaling Q1 and Q2 at 1.8:1.
Amplifier swing is limited by the internal 5.8V supply for
positive outputs and by D1 and D2 when the output goes
low. Low clamp voltage is approximately one diode drop
(≈0.7V – 2mV/°C).
Note that both the FB pin and the V_C pin have other internal
connections. Refer to the frequency shifting and synchro-
nizing discussions.
12
sn1074 1074fds