LTC4266 Datasheet, PDF(11/30 Page) Linear Technology – Quad IEEE 802.3at Power over Ethernet Controller

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LTC4266 Datasheet, PDF (11/30 Pages) Linear Technology – Quad IEEE 802.3at Power over Ethernet Controller

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I2C TIMING DIAGRAMS

LTC4266

SCL

SDA

0 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

START BY

MASTER

ACK BY

SLAVE

ACK BY

SLAVE

ACK BY

SLAVE

STOP BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

FRAME 3

DATA BYTE

4266 F06

Figure 6. Writing to a Register

SCL

SDA

0 1 0 AD3 AD2 AD1 AD0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK

0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

ACK BY

SLAVE

ACK BY

SLAVE

FRAME 2

REPEATED

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

ACK BY

SLAVE

NO ACK BY

MASTER

FRAME 2

DATA BYTE

STOP BY

MASTER

4266 F07

Figure 7. Reading from a Register

SCL

SDA

0 1 0 AD3 AD2 AD1 AD0 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK

START BY

MASTER

FRAME 1

SERIAL BUS ADDRESS BYTE

ACK BY

SLAVE

FRAME 2

DATA BYTE

NO ACK BY

MASTER

STOP BY

MASTER

4266 F08

Figure 8. Reading the Interrupt Register (Short Form)

SCL

SDA

0 0 0 1 1 0 0 R/W ACK 0 1 0 AD3 AD2 AD1 AD0 1 ACK

START BY

MASTER

FRAME 1

ALERT RESPONSE ADDRESS BYTE

ACK BY

SLAVE

NO ACK BY

MASTER

FRAME 2

SERIAL BUS ADDRESS BYTE

STOP BY

MASTER

4266 F09

Figure 9. Reading from Alert Response Address

4266fb

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