LTC4214-1_15 Datasheet, PDF (11/32 Pages) Linear Technology – Negative Low Voltage Hot Swap Controllers

U
OPERATIO
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient cur-
rents from the power bus as they charge. The flow of
current damages the connector pins and glitches the
power bus, causing other boards in the system to reset.
The LTC4214 is designed to turn on a circuit board supply
in a controlled manner, allowing insertion or removal
without glitches or connector damage.
Initial Start-Up
The LTC4214 resides on a removable circuit board and
controls the path between the connector and the load with
an external MOSFET switch (see Figure 1). Both inrush
control and short-circuit protection are provided by the
MOSFET.
A detailed schematic is shown in Figure 2. – 12V and
GND receive power through the longest connector pins
and are the first to connect when the board is inserted. The
GATE pin holds the MOSFET off during this time. UV/OV
determines whether or not the MOSFET should be turned
on based upon internal high accuracy thresholds and an
external divider. UV/OV does double duty by also monitor-
ing whether or not the connector is seated. The top of the
divider detects GND by way of a short connector pin that
is the last to mate during the insertion sequence.
Interlock Conditions
A start-up sequence commences once these “interlock”
conditions are met.
1. The input voltage V_IN exceeds 5.1V (UVLO).
2. The voltage at UV > 2.25V.
LONG
GND
LONG
–12V
BACKPLANE
PLUG-IN BOARD
LTC4214
+
C_LOAD LOAD
4214 F01
Figure 1. Basic LTC4214 Hot Swap Topology
LTC4214-1/LTC4214-2
3. The voltage at OV < 2.85V.
4. The (SENSE – V_EE) voltage is < 50mV (V_CB).
5. The voltage at SS is < 0.2V (20 • V_OS).
6. The voltage on the TIMER capacitor (C_T) is < 1.7V (V_TMRL).
7. The voltage at GATE is < 0.5V (V_GATEL).
The first three conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
TIMER begins the start-up sequence by sourcing 5µA into
C_T. If V_IN, UV or OV falls out of range, the start-up cycle
stops and TIMER discharges C_T to less than 1.7V, then
waits until the aforementioned conditions are once again
met. If C_T successfully charges to 3V, TIMER pulls low
and both SS and GATE pins are released. GATE sources
50µA (I_GATE), charging the MOSFET gate and associated
capacitance. The SS voltage ramp limits V_SENSE to control
the inrush current. PWRGD pulls active low when GATE is
within 2.8V of V_IN and DRAIN is lower than V_DRNL.
Two modes of operation are possible during the time the
MOSFET is first turning on, depending on the values of
external components, MOSFET characteristics and nomi-
nal design current. One possibility is that the MOSFET will
LONG
GND
R_X
10Ω
C_X
100nF
SHORT ^R1
121k
1%
C1
1nF
R2
32.4k
LONG ^1%
–12V
Z1: SMAJ15A
Z1
C_IN
0.1µF
R3
R_IN
10k
470Ω
8
OV
9 _UV
1
V_{IN PWRGD 2}
10
LTC4214-1
TIMER
3
SS
7
DRAIN
C_LOAD +
100µF
TYP
R4
10k
V_EE SENSE GATE
C_SS
22nF
C_T
47nF
5
4
6
C_C
10nF
R_C 10Ω
R_D
475k
R_S
0.025Ω
Q1
IRF7413
4214 F02
GND
EN
V_OUT
Figure 2. –12V, 2A Hot Swap Controller
421412f
11