LTC4099_15 Datasheet, PDF (11/36 Pages) Linear Technology – I2C Controlled USB Power Manager/Charger with Overvoltage Protection

LTC4099
Pin Functions
IRQ (Pin 8): Open-Drain Interrupt Output. The IRQ pin
can be used to generate an interrupt due to a multitude
of maskable status change events within the LTC4099.
See Table 1.
GND (Pin 9, Exposed Pad Pin 21): Ground. The Exposed
Pad and pin must be soldered to the PCB to provide a low
electrical and thermal impedance connection to ground.
IDGATE (Pin 10): Ideal Diode Amplifier Output. This pin
controls the gate of an external P-channel MOSFET tran-
sistor used to supplement the internal ideal diode. The
source of the P-channel MOSFET should be connected to
V_OUT and the drain should be connected to BAT.
BAT (Pin 11): Single-Cell Li-Ion Battery Pin. Depending
on available power and load, a Li-Ion battery on BAT will
either deliver system power to V_OUT through the ideal
diode or be charged from the battery charger.
V_OUT (Pin 12): Output Voltage of the Switching PowerPath
Controller and Input Voltage of the Battery Charger. The
majority of the portable product should be powered from
V_OUT. The LTC4099 will partition the available power be-
tween the external load on V_OUT and the internal battery
charger. Priority is given to the external load and any extra
power is used to charge the battery. An ideal diode from
BAT to V_OUT ensures that V_OUT is powered even if the load
exceeds the allotted power from V_BUS or if the V_BUS power
source is removed. V_OUT should be bypassed with a low
impedance multilayer ceramic capacitor.
V_BUS (Pin 13): Input Voltage for the Switching PowerPath
Controller. V_BUS will usually be connected to the USB port
of a computer or a DC output wall adapter. V_BUS should
be bypassed with a low impedance multilayer ceramic
capacitor.
SW (Pin 14): Switching Regulator Power Transmission
Pin. The SW pin delivers power from V_BUS to V_OUT via the
step-down switching regulator. An inductor should be con-
nected from SW to V_OUT. See the Applications Information
section for a discussion of inductance value.
DV_CC (Pin 15): Logic Reference for the I²C Serial Port. A
0.01µF bypass capacitor is required.
SCL (Pin 16): Clock Input for the I²C Serial Port. The I²C
input levels are scaled with respect to DV_CC.
SDA (Pin 17): Data Input/Output for the I²C Serial Port.
The I²C input levels are scaled with respect to DV_CC.
ACPR (Pin 18): Auxiliary Power Source Present Output
(Active Low). ACPR indicates that the output of an external
high voltage step-down switching regulator connected to
WALL is suitable for use by the LTC4099. ACPR may be
connected to the gate of an external P-channel MOSFET
transistor whose source is connected to V_OUT and whose
drain is connected to WALL. ACPR has a high level of V_OUT
and a low level of GND.
CLPROG (Pin 19): USB Current Limit Program and Monitor
Pin. A 1% resistor from CLPROG to ground determines
the upper limit of the current drawn from the V_BUS pin.
A precise fraction of the input current, h_CLPROG, is sent
to the CLPROG pin when the high side switch is on. The
switching regulator delivers power until the CLPROG pin
reaches 1.18V. Therefore, the current drawn from V_BUS
will be limited to an amount given by h_CLPROG and
R_CLPROG. There are a multitude of ratios for h_CLPROG
available by I²C control, two of which correspond to the
100mA and 500mA USB specifications (see Table 2). A
multilayer ceramic averaging capacitor is also required at
CLPROG for filtering.
OVSENS (Pin 20): Overvoltage Protection Sense Input.
OVSENS should be connected through a 6.2k resistor to
the input power connector and the drain of an external
N‑channel MOSFET pass transistor. When the voltage
on this pin exceeds V_OVCUTOFF, the OVGATE pin will be
pulled to GND to disable the pass transistor and protect
the LTC4099 from potentially damaging high voltage.
4099fd
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