LTC3725_15 Datasheet, PDF (11/20 Pages) Linear Technology – Single-Switch Forward Controller and Gate Driver

LTC3725
APPLICATIO S I FOR ATIO
UVLO
The UVLO pin is connected to a resistive voltage divider
connected to V_IN as shown in Figure 2. The voltage
threshold on the UVLO pin for V_IN rising is 1.242V. To
introduce hysteresis, the LTC3725 draws 4.9µA from the
UVLO pin when V_IN is rising. The hysteresis is therefore
user adjustable and depends on the value of R1. The UVLO
threshold for V_IN rising is:
V_{IN(UVLO, RISING)}
=
(1.242V)R1^{+ R2}
R2
+ R1(4.9µA)
The LTC3725 also has 16mV of voltage hysteresis on the
UVLO pin so that the UVLO threshold for V_IN falling is:
V_{IN(UVLO, FALLING)}
=
(1.226V)R1^{+ R2}
R2
To implement external Run/Stop control, connect a small
NMOS to the UVLO pin as shown in Figure 2. Turning the
NMOS on grounds the UVLO pin and prevents the LTC3725
from running.
V_IN
R1
UVLO
LTC3725
GND
RUN/STOP
R2
CONTROL
(OPTIONAL)
3725 F02
Figure 2. Resistive Voltage Divider for
UVLO and Optional Run/Stop Control
Linear Regulator
The linear regulator eliminates the long start-up times
associated with a conventional trickle charger by using an
external NMOS to quickly charge the capacitor connected
to the V_CC pin.
Note that a trickle charger usually requires a large capaci-
tor to provide holdup for the V_CC pin while the converter
attempts to start. The linear regulator in the LTC3725 can
both charge the capacitor connected to the V_CC pin and
provide primary-side gate-drive bias current. Therefore,
with the linear regulator, the capacitor need only be large
enough to cope with the ripple current from driving the gate
of the primary FET and holdup need not be considered.
The external NMOS for the linear regulator should be a
standard 3V threshold type (i.e. not a logic level thresh-
old). The rate of charge of V_CC from 0V to 8V is controlled
by the LTC3725 to be approximately 45µs regardless of
the size of the capacitor connected to the V_CC pin. The
charging current for this capacitor is approximately:
I_C
=
8V _C
45µs
The safe operating area (SOA) for the external NMOS
should be chosen so that capacitor charging does not
damage the NMOS. Excessive values of capacitor are
unnecessary and should be avoided.
Start-Up Considerations
When used in a self-starting converter with the LTC3706,
the LTC3725 initially begins the soft-start of the converter
in an open-loop fashion. After bias is obtained on the
secondary side, the LTC3706 assumes control and com-
pletes the soft-start interval. In order to ensure that control
is properly transferred from the LTC3725 (primary-side)
to the LTC3706 (secondary-side), it is necessary to limit
the rate of rise on the primary-side soft-start ramp so that
the LTC3706 has adequate time to wake up and assume
control before the output voltage gets too high. This
condition is satisfied for many applications if the following
relationship is maintained:
C_SS,SEC ≤ C_{SS_PRI}
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