LTC3406B-2 Datasheet, PDF (11/16 Pages) Linear Technology – 2.25MHz, 600mA Synchronous Step-Down Regulator in ThinSOT

LTC3406B-2
APPLICATIO S I FOR ATIO
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C_LOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3406B-2. These items are also illustrated graphically
in Figures 5 and 6. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V_IN trace should be kept short, direct and
wide.
2. Does the V_FB pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C_OUT and ground.
3. Does the (+) plate of C_IN connect to V_IN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
V_FB node.
5. Keep the (–) plates of C_IN and C_OUT as close as possible.
1
RUN
5
V_FB
LTC3406B-2
R2
2
–
GND
V_OUT
+
C_OUT
L1
3 _SW
V_IN ⁴
C_IN
BOLD LINES INDICATE HIGH CURRENT PATHS
R1
C_FWD
+
V_IN
–
3406B F05
Figure 5. LTC3406B-2 Layout Diagram
VIA TO GND
V_OUT
VIA TO V_IN
PIN 1
L1 ^SW
LTC3406B-2
R1
R2
C_FWD
V_IN
VIA TO V_OUT
C_OUT
C_IN
GND
Figure 6. LTC3406B-2 Suggested Layout
3406B F06
sn3406b2 3406b2fs
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