LTC3406-1.5_15 Datasheet, PDF (11/16 Pages) Linear Technology – 1.5MHz, 600mA Synchronous Step-Down Regulator in ThinSOT

LTC3406
LTC3406-1.5/LTC3406-1.8
APPLICATIO S I FOR ATIO
The junction temperature, T_J, is given by:
T_J = T_A + T_R
where T_A is the ambient temperature.
As an example, consider the LTC3406 in dropout at an
input voltage of 2.7V, a load current of 600mA and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the R_DS(ON) of the
P-channel switch at 70°C is approximately 0.52Ω. There-
fore, power dissipated by the part is:
P_D = I_LOAD2 • R_DS(ON) = 187.2mW
For the SOT-23 package, the θ_JA is 250°C/ W. Thus, the
junction temperature of the regulator is:
T_J = 70°C + (0.1872)(250) = 116.8°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R_DS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to (∆I_LOAD • ESR), where ESR is the effective series
resistance of C_OUT. ∆I_LOAD also begins to charge or
discharge C_OUT, which generates a feedback error signal.
The regulator loop then acts to return V_OUT to its steady-
state value. During this recovery time V_OUT can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C_OUT, causing a rapid drop in V_OUT. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25 • C_LOAD).
Thus, a 10µF capacitor charging to 3.3V would require a
250µs rise time, limiting the charging current to about
130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3406. These items are also illustrated graphically in
Figures 5 and 6. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V_IN trace should be kept short, direct and
wide.
2. Does the V_FB pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be con-
nected between the (+) plate of C_OUT and ground.
3. Does the (+) plate of C_IN connect to V_IN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
4. Keep the switching node, SW, away from the sensitive
V_FB node.
5. Keep the (–) plates of C_IN and C_OUT as close as possible.
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