LTC3240-3.3_15 Datasheet, PDF (11/12 Pages) Linear Technology – 3.3V/2.5V Step-Up/ Step-Down Charge Pump DC/DC Converter

APPLICATIO S I FOR ATIO
3.0
θ_JA = 80°C/W
2.5
2.0
THERMAL
SHUTDOWN
1.5
T_J = 160°C
1.0
RECOMMENDED
OPERATION
0.5
T_J = 125°C
0
– 50 – 25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE (°C)
LT3240 F05
Figure 5. Maximum Power Dissipation vs Ambient Temperature
LTC3240-3.3/LTC3240-2.5
This derating curve assumes a maximum thermal resis-
tance, θ_JA, of 80°C/W for the 2 × 2 DFN package. This can
be achieved from a printed circuit board layout with a solid
ground plane and a good connection to the ground pins of
LTC3240 and the Exposed Pad of the DFN package.
It is recommended that the LTC3240 be operated in the
region corresponding to T_J ≤ 125°C for continuous opera-
tion as shown in Figure 5. Short term operation may be
acceptable for 125°C ≤ T_J ≤ 160°C but long term operation
in this region should be avoided as it may reduce the life of
the part or cause degraded performance. For T_J ≥ 160°C,
the part will be in thermal shutdown.
PACKAGE DESCRIPTIO
DC Package
6-Lead Plastic DFN (2mm × 2mm)
(Reference LTC DWG # 05-08-1703)
2.50 ±0.05
1.15
±0.05
0.61 ±0.05
(2 SIDES)
0.675 ±0.05
PACKAGE
OUTLINE
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.25 ± 0.05
0.50 BSC
1.42 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.200 REF
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WCCD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
R = 0.115
TYP
0.56 ± 0.05
4
(2 SIDES)
0.38 ± 0.05
6
2.00 ±0.10
(4 SIDES)
0.75 ±0.05
0.00 – 0.05
PIN 1
CHAMFER OF
EXPOSED PAD
3
1
(DC6) DFN 1103
0.25 ± 0.05
0.50 BSC
1.37 ±0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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