LTC3220-1_15 Datasheet, PDF (11/20 Pages) Linear Technology – 360mA Universal 18-Channel LED Driver

LTC3220/LTC3220-1
OPERATION
sub-address register is then written to, followed by the
data register. Each data register has a sub-address. After
the data register has been written a load pulse is created
after the stop bit. The load pulse transfers all of the data
held in the data registers to the DAC registers. The stop
bit can be delayed until all of the data master registers
have been written. At this point the LED current will be
changed to the new settings. The serial port uses static
logic registers so there is no minimum speed at which it
can be operated.
I²C Interface
The LTC3220/LTC3220-1 communicate with a host (master)
using the standard I²C 2-wire interface. The Timing Diagram
(Figure 3) shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus accelerator,
are required on these lines.
The LTC3220/LTC3220-1 are receive-only (slave) devices.
There are two I²C addresses available. The LTC3220 I²C
address is 0011100 and the LTC3220-1 I²C address is
0011101. The I²C address is the only difference between
the LTC3220 and LTC3220-1.
Write Word Protocol Used By the LTC3220/LTC3220-1
1
7
11
8
1
8
11
S Slave Address Wr A *Sub-Address A Data Byte A P**
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge,
P = Stop Condition
*The sub-address uses only the first 5 bits, D0, D1, D2, D3 and D4.
**Stop can be delayed until all of the data registers have been written.
LTC3220
00
ADDRESS
1110
WR
00
SUB-ADDRESS
S7 S6 S5 S4 S3 S2 S1 S0
DATA BYTE
76543210
LTC3220-1
00
ADDRESS
1110
WR
10
START
STOP
SDA
0 0 1 1 1 0 0 0 ACK S7 S6 S5 S4 S3 S2 S1 S0 ACK 7 6 5 4 3 2 1 0 ACK
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 89 1 2 3 4 5 6 7 8 9
3220 FO2
Figure 2. Bit Assignments
SDA
t_LOW
t_{SU, DAT}
SCL
t_{HD, STA}
START
CONDITION
t_HIGH
t_r
t_f
t_{HD, DAT}
t_{SU, STA}
t_{HD, STA}
t_SP
REPEATED START
CONDITION
Figure 3. Timing Parameters
t_BUF
t_{SU, STO}
3220 F03
STOP
CONDITION
START
CONDITION
32201fc
11