LTC2923_15 Datasheet, PDF (11/20 Pages) Linear Technology – Power Supply Tracking Controller

LTC2923
APPLICATIO S I FOR ATIO
3-Step Design Procedure
The following 3-step procedure allows one to complete a
design for any of the tracking or sequencing profiles
shown in Figures 1 to 4. A basic three supply application
circuit is shown in Figure 9.
1. Set the ramp rate of the master signal.
Solve for the value of C_GATE, the capacitor on the GATE
pin, based on the desired ramp rate (V/s) of the master
supply, S_M.
C_GATE
=
I_GATE
S_M
where I_GATE ≈ 10µA
(1)
If the external FET has a gate capacitance comparable to
C_GATE, then the external capacitor’s value should be
reduced to compensate for the FET’s gate capacitance.
If no external FET is used, tie the GATE and RAMP pins
together.
2. Solve for the pair of resistors that provide the desired
ramp rate of the slave supply, assuming no delay.
Choose a ramp rate for the slave supply, S_S. If the slave
supply ramps up coincident with the master supply or
with a fixed voltage offset, then the ramp rate equals the
master supply’s ramp rate. Be sure to use a fast enough
ramp rate for the slave supply so that it will finish
ramping before the master supply has reached its final
supply value. If not, the slave supply will be held below
the intended regulation value by the master supply. Use
the following formulas to determine the resistor values
for the desired ramp rate, where R_FB and R_FA are the
feedback resistors in the slave supply and V_FB is the
feedback reference voltage of the slave supply:
R_TB
=
R_FB
•
S_M
S_S
(2)
R_TA^′
=
V_FB
R_FB
+
V_TRACK
V_{FB –} V_TRACK
R_FA R_TB
(3)
where V_TRACK ≈ 0.8V.
Note that large ratios of slave ramp rate to master ramp
rate, S_S/S_M, may result in negative values for R_TA′. If
sufficiently large delay is used in step 3, R_TA will be
positive, otherwise S_S/S_M must be reduced.
3. Choose R_TA to obtain the desired delay.
If no delay is required, such as in coincident and
ratiometric tracking, then simply set R_TA = R_TA′. If a
delay is desired, as in offset tracking and supply se-
quencing, calculate R_TA′′ to determine the value of R_TA
where t_D is the desired delay in seconds.
R_TA^′′
=
V_TRACK • R_TB
t_D • S_M
(4)
R_TA = R_TA′||R_TA′′
(5)
the parallel combination of R_TA′ and R_TA′′
As noted in step 2, small delays and large ratios of slave
ramp rate to master ramp rate (usually only seen in
sequencing) may result in solutions with negative values
for R_TA. In such cases, either the delay must be increased
or the ratio of slave ramp rate to master ramp rate must be
reduced.
Q1
V_IN
MASTER
0.1µF
10Ω ^CGATE
V_IN
R_ONB
R_ONA
V_CC GATE RAMP
ON
FB1
LTC2923
R_TB1
RAMPBUF
TRACK1
R_TA1 ^RTB2
TRACK2
FB2
R_TA2
GND
IN
DC/DC
FB
OUT
R_FA1
R_FB1
V_IN
IN
DC/DC
FB
OUT
R_FB2
R_FA2
2923 F09
SLAVE1
SLAVE2
Figure 9. Three Supply Application
2923fa
11