LTC2392-16 Datasheet, PDF (11/24 Pages) Linear Technology – 16-Bit, 500ksps SAR ADC with 94dB SNR

LTC2392-16
Applications Information
OVERVIEW
The LTC2392-16 is a low noise, high speed 16-bit suc-
cessive approximation register (SAR) ADC. Operating
from a single 5V supply, the LTC2392-16 supports a
large ±4.096V fully differential input range, making it ideal
for high performance applications which require a wide
dynamic range. The LTC2392-16 achieves ±2LSB INL max,
no missing codes at 16 bits and 94dB SNR (typ).
The LTC2392-16 includes a precision internal reference with
a guaranteed 0.5% initial accuracy and a ±20ppm/°C (max)
temperature coefficient. Fast 500ksps throughput with no
cycle latency in both parallel and serial interface modes
makes the LTC2392-16 ideally suited for a wide variety
of high speed applications. An internal oscillator sets the
conversion time, easing external timing considerations.
The LTC2392-16 dissipates only 110mW at 500ksps, while
both nap and sleep power-down modes are provided to
further reduce power during inactive periods.
CONVERTER OPERATION
The LTC2392-16 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN⁺ and IN^– pins
to sample the differential analog input voltage. A falling
edge on the CNVST pin initiates a conversion. During the
conversion phase, the 16-bit CDAC is sequenced through a
successive approximation algorithm, effectively comparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g., V_REF/2, V_REF/4 … V_REF/65536)
using the differential comparator. At the end of conversion,
the CDAC output approximates the sampled analog input.
The ADC control logic then prepares the 16-bit digital
output code for parallel or serial transfer.
TRANSFER FUNCTION
The LTC2392-16 digitizes the full-scale voltage of 2 • V_REF
into 2¹⁶ levels, resulting in an LSB size of 125µV when V_REF
= 4.096V. The ideal transfer function for two’s complement
is shown in Figure 2. The OB/2C pin selects either offset
binary or two’s complement format.
011...111
011...110
000...001
000...000
111...111
111...110
BIPOLAR
ZERO
100...001
100...000
FSR = +FS – –FS
1LSB = FSR/65536
–FSR/2
–1 0V 1
LSB LSB
INPUT VOLTAGE (V)
FSR/2 – 1LSB
239216 F02
Figure 2. LTC2392-16 Two’s Complement Transfer Function
ANALOG INPUT
The analog inputs of the LTC2392-16 are fully differential
in order to maximize the signal swing that can be digitized.
The analog inputs can be modeled by the equivalent circuit
shown in Figure 3. The diodes at the input provide ESD pro-
tection. The analog inputs should not exceed the supply or
go below ground. In the acquisition phase, each input sees
approximately 40pF (C_IN) from the sampling CDAC in series
with 50Ω (R_IN) from the on-resistance of the sampling
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw only one small current spike
while charging the C_IN capacitors during acquisition.
During conversion, the analog inputs draw only a small
leakage current.
AVP
IN⁺
R_IN ^CIN
AVP
IN^–
R_IN ^CIN
BIAS
VOLTAGE
239216 F03
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2392-16
239216f
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