LTC1745 Datasheet, PDF (11/20 Pages) Linear Technology – Low Noise,12-Bit, 25Msps ADC

LTC1745
APPLICATIO S I FOR ATIO
CONVERTER OPERATION
As shown in Figure 1, the LTC1745 is a CMOS pipelined
multistep converter. The converter has four pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later, see the Timing Diagram section.
The analog input is differential for improved common
mode noise immunity and to maximize the input range.
Additionally, the differential input drive will reduce even
order harmonics of the sample-and-hold circuit. The en-
code input is also differential for improved common mode
noise immunity.
The LTC1745 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For
brevity, the text will refer to ENC greater than ENC as ENC
high and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
A_IN+
INPUT
A_IN–
S/H
FIRST STAGE
5-BIT
PIPELINED
ADC STAGE
SECOND STAGE
4-BIT
PIPELINED
ADC STAGE
THIRD STAGE
4-BIT
PIPELINED
ADC STAGE
FOURTH STAGE
4-BIT
FLASH
ADC
V_CM
4.7µF
2.35V
REFERENCE
RANGE
SELECT
REF
SENSE
BUF
SHIFT REGISTER AND CORRECTION
INTERNAL
REFERENCES TO ADC
INTERNAL
CLOCK SIGNALS
DIFFERENTIAL
DIFF
REF
AMP
INPUT
LOW JITTER
CLOCK
CONTROL
LOGIC
DRIVER
REFLB REFHA REFLA REFHB ENC ENC
MSBINV
OE
4.7µF
0.1µF
0.1µF
1µF
1µF
Figure 1. Functional Block Diagram
OUTPUT
DRIVERS
OV_DD
0.5V TO
5V
OF
D11
•••
D0
CLKOUT
1745 F01
OGND
1745f
11