LTC1606_1 Datasheet, PDF (11/16 Pages) Linear Technology – 16-Bit, 250ksps, Single Supply ADC

LTC1606
APPLICATIO S I FOR ATIO
Timing and Control
Conversion start and data read are controlled by two
digital inputs: CS and R/C. To start a conversion and put
the sample-and-hold into the hold mode, bring CS and
R/C low for no less than 40ns. Once initiated, it cannot be
restarted until the conversion is complete. Converter
status is indicated by the BUSY output and this is low while
the conversion is in progress.
There are two modes of operation. The first mode is shown
in Figure 8. The digital input R/C is used to control the start
of conversion. CS is tied low. When R/C goes low, the
sample-and-hold goes into the hold mode and a conver-
sion is started. BUSY goes low and stays low during the
conversion and will go back high after the conversion has
been completed and the internal output shift registers
have been updated. R/C should remain low for no less than
40ns. During the time R/C is low, the digital outputs are in
a Hi-Z state. R/C should be brought back high within 1µs
after the start of the conversion to ensure that no errors
occur in the digitized result. The second mode, shown in
Figure 9, uses the CS signal to control the start of a
conversion and the reading of the digital output. In this
mode the R/C input signal should be brought low no less
than 10ns before the falling edge of CS. The minimum
pulse width for CS is 40ns. When CS falls, BUSY goes low
and will stay low until the end of the conversion. BUSY will
go high after the conversion has been completed. The new
data is valid when CS is brought back low again to initiate
a read. Again, it is recommended that both R/C and CS
return high within 1µs after the start of the conversion.
Output Data
The output data can be read as a 16-bit word or it can be
read as two 8-bit bytes. The format of the output data is
two’s complement. The digital input pin BYTE is used to
control the two byte read. With the BYTE pin low, the first
eight MSBs are output on the D15 to D8 pins and the eight
LSBs are output on the D7 to D0 pins. When the BYTE pin
is taken high, the eight LSBs replace the eight MSBs
(Figure 10).
R/C
BUSY
t₁
t₃
t₁₁
t₂
t₄
MODE
t₆
ACQUIRE
DATA MODE
PREVIOUS
DATA VALID
t₇
CONVERT
t_CONV
t₉
Hi-Z
PREVIOUS
DATA VALID
NOT VALID
t₅
ACQUIRE
t_ACQ
DATA
VALID
t₈
CONVERT
Hi-Z
DATA
VALID
1606 • F08
Figure 8. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low)
1606fa
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