LTC1335_15 Datasheet, PDF (11/20 Pages) Linear Technology – RS232/EIA562/RS485 Transceivers

LTC1321/LTC1322/LTC1335
BLOCK DIAGRA SM
LTC1322/LTC1335 Interface Configuration With Loopback
PORT 1 = EIA562 MODE
PORT 2 = EIA562 MODE
PORT 1 = RS485 MODE
PORT 2 = EIA562 MODE
PORT 1 = EIA562 MODE
PORT 2 = RS485 MODE
PORT 1 = RS485 MODE
PORT 2 = RS485 MODE
*V_DD/OE ^{1 *}
24 _{VCC *VDD/OE} 1 _*
24 _{VCC *VDD/OE}
23 _RB1
1*
24 _{VCC *VDD/OE} 1 _*
24 _VCC
23 _RB1
4
Z1
5
Y1
SEL1 ⁶
7
SEL2
8
Y2
Z2 ⁹
12
GND
23
R_B1
22 _RA1
21 _DZ1
20 _DY1
19
LB
18 _ON
17 _DY2
16 _DZ2
15 _RA2
14
13
R_B2
V_EE
Z1 ⁴
Y1 ⁵
**SEL1 ⁶
7
SEL2
8
Y2
9
Z2
GND ¹²
22
R_A1
21
DE1
20
D_Y1
19 _LB
18 _ON
17 _DY2
16
D_Z2
15 _RA2
14
13
R_B2
V_EE
4
Z1
5
Y1
SEL1 ⁶
**SEL2 ⁷
8
Y2
9
Z2
12
GND
23
R_B1
22 _RA1
4
Z1
21 _DZ1
20 _DY1
Y1 ⁵
19
LB
**SEL1
6
7
18
**SEL2
ON
17 _DY2
8
Y2
16 _DE2
15
R_A2
14
13
R_B2
V_EE
9
Z2
12
GND
22 _RA1
21 _DE1
20 _DY1
19
LB
18
ON
17 _DY2
16 _DE2
15
R_A2
14
13
R_B2
V_EE
* FOR LTC1322 ONLY, PIN 1 IS V_DD, AND OE IS ALWAYS ENABLED.
FOR LTC1335, PIN 1 IS OE, AND V_DD IS CONNECTED TO V_CC.
** SEL1/SEL2 = V_CC.
1322/35 BD02
TEST CIRCUITS
Y
R
V_OD
R ^VOC
Z
1321/22/35 F01
Figure 1. RS485 Driver
Test Load
0V
SEL
D
Y OR Z
C_L
R_L
1321/22/35 F04
Figure 4. EIA/TIA-562 Driver
Timing Test Circuit
3V
SEL Y
D
R_L
DE ^Z
3V
3V
C_L
A
SEL
R
C_L
B ^OE
15pF
0V
1321/22/35 F02
Figure 2. RS485 Driver/Receiver
Timing Test Circuit
0V
0V
SEL
SEL
D
Y OR Z A OR B
R
OE
15pF
0V
1321/22/35 F05
Figure 5. EIA/TIA-562 Receiver
Timing Test Circuit
DR OUT
V_CC
S1
500Ω
C_L
S2
1321/22/35 F03
Figure 3. RS485 Driver Output
Enable/Disable Timing Test Load
V_CC
RX OUT
S1
1k
C_L
S2
1321/22/35 F06
Figure 6. Receiver Output
Enable/Disable Timing Test Load
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