LT6556_15 Datasheet, PDF (11/16 Pages) Linear Technology – 750MHz Gain of 1 Triple 2:1Video Multiplexer

LT6556
APPLICATIO S I FOR ATIO
enabled output. However, since the disabled LT6556 and its
traces have around 6pF of capacitance, it may be desirable
to resistively isolate the outputs of each channel to maintain
flat frequency response as shown in the graph labeled
“Maximum Capacitive Load vs Output Series Resistor” in
the Typical Performance Characteristics section.
ESD Protection
The LT6556 has reverse-biased ESD protection diodes on all
pins. If any pins are forced a diode drop above the positive
supply or a diode drop below the negative supply, large
currents may flow through these diodes. If the current is
kept below 10mA, no damage to the devices will occur.
TYPICAL APPLICATIO
RGB Multiplexer Demo Board
The DC892A Demo Board illustrates optimal routing,
bypassing and termination using the LT6556 as an
RGB video multiplexer. The schematic is shown in Figure 6.
All inputs and outputs are routed to have a characteristic
impedance of 75Ω and 75Ω input shunt and output series
terminations are connected as close to the part as pos-
sible. The board is fabricated with four layers with internal
ground and power planes.
While the 75Ω back termination resistors at the outputs
of the LT6556 minimize signal reflections in the output
traces and isolate the part from any capacitive loading in
those traces, they also contribute to gain error if the out-
put is not terminated with high impedance. For example,
if the output is terminated with a 1k load, the 75Ω back
termination will cause a 7% gain error. Decreasing the
value of the back termination resistors will decrease the
signal attenuation but may compromise the AC response.
However, connecting the LT6556 output pins to the output
traces on the DC892A board without some series resistance
is not recommended; 10Ω to 20Ω is generally sufficient.
Figures 7 and 8 show the top and bottom side board layout
and placement.
J1
50Ω BNC
1
EN
5 4 3 2 DGND
BNC × 6
5 JP12
IN1A 4
1 L1 Z = 75
3
2
5 JP13
IN2A 4
1 L1 Z = 75
3
2
5 JP14
IN3A 4
1 L1 Z = 75
3
2
5 JP5
IN1B 4
1 L1 Z = 75
3
2
5 JP6
IN2B 4
1 L1 Z = 75
3
2
5 JP7
IN3B 4
1 L1 Z = 75
3
2
E1
EN
JP1
3 ^CONTROL1
2
EXT ENABLE
E2
DGND
JP2
3 ^DGND 1
2
FLOAT AGND
E5
V_REF
JP5
3 ^VREF 1
2
EXT GND
R10 R11 R12 R4 R5
75Ω 75Ω 75Ω 75Ω 75Ω
J3
BANANA JACK
AGND
E3
AGND
Z = 50
R8
50Ω
OPT
E4
SEL A/B
Z = 50
R9
50Ω
OPT
2
R7
3 ^{A B} 1 ^20k
V_CC
JP4
SEL
J8
50Ω BNC
1
SEL A/B
DGND ^{5 4 3 2}
22
U1 LT6556CUF
IN1A
V⁺
21
DGND 23 _DGND
EN ^{20 EN}
24
IN2A
19 SEL
SEL A/B
V_REF
1 _VREF
V^{+ 18}
2
IN3A
17
OUT1
3
AGND1
V^{– 16}
5
IN1B
15
OUT2
6
AGND2
V^{+ 14}
7
IN2B
13
OUT3
8
AGND3
V^{– 12}
9
IN3B
V^{+ 11}
R6
75Ω
4 _V–
V^–
V^{+ 10}
25
C1
4700pF
SINGLE DUAL
2
1 _JP3 3
SUPPLY
C5
4700pF
NOTE:
470pF BYPASS CAPACITORS LOCATED
AS CLOSE TO PINS AS POSSIBLE
C2
470pF
C6
470pF
C3
470pF
C9
10μF
16V
1206
C10
4700pF
C4
10μF
16V
1206
J2
BANANA JACK
V_CC
C7
3.3V TO 5V
0.33μF
10V _VCC
R1
75Ω _{Z = 75}
R2
75Ω _{Z = 75}
R3
75Ω _{Z = 75}
BNC × 3
J9 5
L2 1
4
3
2
J10 5
L2 1
4
3
2
L2 1 ^J11
5
4
3
2
OUT1
OUT2
OUT3
C8
0.33μF
10V
J4
BANANA JACK
V_EE
–3.3V TO –5V
V_EE
6556 F06
Figure 6. Demo Board Schematic
6556f
11