LT6550 Datasheet, PDF (11/16 Pages) Linear Technology – 3.3V Triple and Quad Video Amplifiers

LT6550/LT6551
APPLICATIO S I FOR ATIO
Amplifier Characteristics
Figure 1 shows a simplified schematic of one channel of
the LT6551 quad. Resistors RF and RG provide an internal
gain of 2. (The LT6550 triple is a slight variation with the
gain setting resistor, RG, connected to a separate ground
pin). The input stage consists of transistors Q1 to Q8 and
resistor R1. This topology allows for high slew rates at low
supply voltages. There are back-to-back series diodes, D1
to D4, across the + and – inputs of each amplifier to limit
the differential input voltage to ±1.4V. R_IN limits the
current through these diodes if the input differential volt-
age exceeds ±1.4V. The input stage drives the degenera-
tion resistors of PNP and NPN current mirrors, Q9 to Q12,
that convert the differential signals into a single-ended
output. The complementary drive generator supplies cur-
rent to the output transistors that swing from rail-to-rail.
Input Voltage Range
The input voltage range is V_EE to (V_CC – 1.75V) over
temperature. If the device is operated on a single 3V supply
the maximum input is (3V – 1.75V) or 1.25V, and the
internal gain of two will set the output voltage to 2.5V.
Increasing the input beyond 1.25V will force the device out
of its linear range, no longer a gain of 2, and the output will
not increase beyond 2.5V. At a higher supply voltage, i.e.
5V, the maximum input voltage is 5V – 1.75V or 3.25V.
However, due to the internal gain of 2, the output will clip
with a lower input voltage. For linear unclipped operation
the minimum input voltage is (V_OUT Min)/2 and the maxi-
mum input voltage is (V_OUT Max)/2 or (V_CC – 1.75V),
whichever is less.
ESD
The LT6550/LT6551 have reverse-biased ESD protection
diodes on all inputs and outputs as shown in Figure 1. If
these pins are forced beyond either supply, unlimited
current will flow through these diodes. If the current is
limited to 10mA or less, no damage to the device will
occur.
RF
450Ω
I1
V⁺
DESD1
IN
DESD2
R_IN
225Ω
D1
GND
D2
Q2
+ _Q1
D3
D4
Q3 Q5
R1
Q4 Q6
I2
Q7
Q8 ^–
I3
R2
R3
V⁺
Q13
Q9
Q10
CM
COMPLEMENTARY
DRIVE
GENERATOR
Q11
Q12
V⁺
DESD3
OUT
DESD4
GND
RG
450Ω
I4
R4
R5
Q14
GND
6551 F01
Figure 1. LT6551 Simplified Schematic
65501f
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