LT1306_15 Datasheet, PDF (11/16 Pages) Linear Technology – Synchronous, Fixed Frequency Step-Up DC/DC Converter

LT1306
APPLICATIONS INFORMATION
where
R_L
=
Maximum Load
=
Output Voltage
Maximum DC Load Current
D_MAX = Maximum Converter Duty Cycle
= ^{VO – VIN(MIN) + 0.5}
V_O + 0.1
There is also a second pole at the current loop crossover
frequency ω_C (Figure 6). ω_Z is much lower in frequency
than ω_C. The loop is compensated by adjusting the midband
gain with resistor R3 (Figure 7) so that the overall loop gain
crosses 0dB before the minimum frequency RHP zero
(i.e., corresponding to the highest duty ratio). The value of
R3 can be estimated with the fromula:
R3 = ^{390VO(1– DMAX )CORL}
L
Due to the low transconductance of the error amplifier, the
gain setting resistor R3 is AC-coupled with capacitor C_Z.
This prevents R3 from inducing an offset to the input of the
error amplifier. It also creates a pole at DC and a low
frequency zero.
The amplitude response of the error amplifier with the
compensation network shown is:
The low frequency zero 1/R3C_Z of the compensation
network is placed at ω_P/2.
C_Z
=
2
R3ω_P
The capacitor C_P ensures adequate gain margin beyond
the RHP zero. The high frequency pole 1/R3C_P of the
amplifier frequency response is placed beyond ω_Z.
C_P
=
1
3ω_ZR3
Higher output filter capacitance rolls off the gain response
from a lower corner frequency so higher midband gain is
required in the compensation network to make the overall
loop gain cross 0dB just below ω_Z.
Layout Consideration
To minimize EMI and high frequency resonances, it is
essential to keep the SW and the CAP trace leads as short
as possible. The input and the output bypass capacitors
C_IN and C_OUT should be placed close to the IC package and
soldered to the ground plane. A ground plane under the
switching regulator is highly recommended. Figure 8
shows a suggested component placement and PC board
layout.
( ) _VˆC
[ ^{( )}] ^VˆO
=

g_{m}
R2 ^
R1+ R2
1+ S • R3 • C_Z
S • C_Z 1+ S • R3 • C_P
C_Z >> C_P
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