LT1103_15 Datasheet, PDF (11/32 Pages) Linear Technology – Offline Switching Regulator

LT1103/LT1105
PIN FUNCTIONS
LT1103
FB: The Feedback pin is the inverting input to the sampling
error amplifier. The noninverting input is tied to a 4.5V
reference. The FB pin is used for output voltage sensing.
The input bias current is a function of the control pin V_C
voltage and can be used for load regulation compensation
by including a resistor in series with the FB pin. The
sampling error amplifier has a typical g_m of 0.012 mhos
and the output of the sampling error amplifier has asym-
metrical slew rate to reduce overshoot during start-up
conditions or following the release of an output overload.
V_C: The V_C control pin is used for frequency compensa-
tion, current limiting and shutdown. It is the high imped-
ance output of the sampling error amplifier and the input
of the current limit comparator.
GND: The Ground pin acts as both the negative sense
point for the internal sampling error amplifier feedback
signal and as the high current path for the 2A switch.
Also, the case of the 7-lead TO-220 is connected to
ground. Proper connections to ground for signal paths
and high current paths must be made in order to insure
good load regulation.
OSC: The Oscillator pin sets the operating frequency of the
regulator with one external capacitor to ground. Maximum
duty cycle can also be adjusted by using an external
resistor to alter the charge/discharge ratio.
V_IN: The Input Supply pin is designed to operate with
voltages of 12V to 30V. The supply current is typically
200µA up to the start-up threshold of 16V. Normal oper-
ating supply current is fairly flat at 18mA down to the
shutdown threshold of 7V. Switching is inhibited for V_IN
less than 12V due to the gate drive detection circuit.
15V: A 15V reference is used to bias the gate of an external
power FET. The voltage temperature coefficient is typically
3mV/°C and the output can source 30mA. Typical dropout
voltage is 1.5V for V_IN less than 17V and 30mA of load
current.
V_SW: The Switch Output pin is the collector of the internal
NPN power switch. This pin has a typical ON resistance of
0.4Ω and a minimum breakdown voltage of 50V. This pin
also ties to the FET gate drive detection circuit.
LT1105
All functions on the LT1105 are equivalent to the LT1103
with the exception of the V_SW pin and the I_LIM pin and the
availability of the OVLO, 5V, and SS functions.
OVLO: The Overvoltage Lockout pin inhibits switching
when the pin is pulled above its threshold voltage of 2.5V.
OVLO is implemented with a resistor divider network from
the rectified DC line and is used to protect the external FET
from an overvoltage condition in the off state. This func-
tion is only available on the 14-lead PDIP.
5V: A 5V reference is available to power primary-side
circuitry. The temperature coefficient is typically
50ppm/°C and the output can source 25mA. This func-
tion is only available on the 14-lead PDIP.
SS: The Soft-Start pin is used to either program start-up
time with a capacitor to ground or to set external current
limit with a resistor divider. The SS pin has a 40µA pull-up
current and is reset to 0V by a 1mA pull-down current
during start-up and shutdown. This function is only avail-
able on the 14-lead PDIP.
V_SW: The Switch Output pin is the output of a 1A NPN
totem-pole stage. The V_SW pin turns the external FET on by
pulling its gate high. Break-Before-Make action of 200ns
on each switch edge is built in to eliminate cross conduc-
tion currents.
I_LIM: The I_LIM pin is the input to the current limit amplifier
and requires the use of a noninductive, power sense
resistor from I_LIM to ground to set current limit. The typical
current limit threshold voltage is 350mV. The typical input
bias current is 100µA out of the pin.
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