LTC3856 Datasheet, PDF (10/40 Pages) Linear Technology – 2-Phase Synchronous Step-Down DC/DC Controller with Diffamp

LTC3856
Pin Functions (TSSOP/QFN)
INTV_CC (Pin 29/Pin 21): Internal 5V Regulator Output. The
control circuits are powered from this voltage. Decouple
this pin to PGND with a minimum of 4.7µF low ESR tan-
talum or ceramic capacitor.
V_IN (Pin 30/Pin 22): Main Input Supply. Decouple this pin
to PGND with a capacitor (0.1µF to 1µF).
BG1, BG2 (Pins 31, 27/Pins 23, 19): Bottom Gate Driver
Outputs. These pins drive the gates of the bottom N-chan-
nel MOSFETs between INTV_CC and PGND.
PGND1, PGND2 (Pins 32, 26) TSSOP Package: Power
Ground Pin. Connect this pin closely to the sources of the
bottom N-channel MOSFETs, the (–) terminal of CV_CC and
the (–) terminal of C_IN.
BOOST1, BOOST2 (Pins 33, 24/Pins 24, 18): Boosted
Floating Driver Supplies. The (+) terminal of the boot-
strap capacitors connect to these pins. These pins swing
from a diode voltage drop below INTV_CC up to V_IN +
INTV_CC.
SGND/PGND (Exposed Pad Pin 33) QFN Package: Signal
Ground and Power Ground. Connect this pin closely to
the sources of the bottom N-channel MOSFETs, the (–)
terminal of CV_CC and the (–) terminal of C_IN. All small-signal
components and compensation components should also
connect to this ground.
TG1, TG2 (Pins 35, 23/Pins 25, 17): Top Gate Driver
Outputs. These are the outputs of floating drivers with
a voltage swing equal to INTV_CC superimposed on the
switch nodes voltages.
SW1, SW2 (Pins 36, 22/Pins 26, 16): Switch Node
Connections to Inductors. Voltage swing at these pins
is from a Schottky diode (external) voltage drop below
ground to V_IN.
CLKOUT (Pin 37/Pin 27): Clock output with phase change-
able by PHASMD to enable usage of multiple LTC3856 ICs
in multiphase systems.
PLLIN (Pin 38/Pin 28): External Synchronization Pin. A
clock on the pin synchronizes the internal oscillator with
the clock on this pin.
SGND (Exposed Pad Pin 39) TSSOP Package: The exposed
pad must be soldered to the PCB.
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