LTC3406-1.8_15 Datasheet, PDF (10/16 Pages) Linear Technology – 1.5MHz, 600mA Synchronous Step-Down Regulator in ThinSOT

LTC3406
LTC3406-1.5/LTC3406-1.8
APPLICATIO S I FOR ATIO
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3406 circuits: V_IN quiescent current and I²R
losses. The V_IN quiescent current loss dominates the
efficiency loss at very low load currents whereas the I²R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 4.
1
0.1
0.01
0.001
V_OUT = 1.2V
V_OUT = 1.5V
V_OUT = 1.8V
V_OUT = 2.5V
0.0001
0.00001
0.1
1
10
100
LOAD CURRENT (mA)
1000
3406 F04
Figure 4. Power Lost vs Load Current
1. The V_IN quiescent current is due to two components:
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge, dQ, moves from V_IN to ground. The resulting
dQ/dt is the current out of V_IN that is typically larger than
the DC bias current. In continuous mode, I_GATECHG =
f(Q_T + Q_B) where Q_T and Q_B are the gate charges of the
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V_IN and thus
their effects will be more pronounced at higher supply
voltages.
2. I²R losses are calculated from the resistances of the
internal switches, R_SW, and external inductor R_L. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R_DS(ON) and the duty cycle
(DC) as follows:
R_SW = (R_DS(ON)TOP)(DC) + (R_DS(ON)BOT)(1 – DC)
The R_DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I²R losses, simply add R_SW to
R_L and multiply the result by the square of the average
output current.
Other losses including C_IN and C_OUT ESR dissipative
losses and inductor core losses generally account for less
than 2% total additional loss.
Thermal Considerations
In most applications the LTC3406 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3406 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such
as in dropout, the heat dissipated may exceed the maxi-
mum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
To avoid the LTC3406 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T_R = (P_D)(θ_JA)
where P_D is the power dissipated by the regulator and θ_JA
is the thermal resistance from the junction of the die to the
ambient temperature.
3406fa
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