LTC3405A-1.375_15 Datasheet, PDF (10/12 Pages) Linear Technology – 1.375V, 1.5MHz, 300mA Synchronous Step-Down Regulators in ThinSOT

LTC3405A-1.375
APPLICATIO S I FOR ATIO
where P_D is the power dissipated by the regulator and θ_JA
is the thermal resistance from the junction of the die to the
ambient temperature.
The junction temperature, T_J, is given by:
T_J = T_A + T_R
where T_A is the ambient temperature.
As an example, consider the LTC3405A-1.375 with an
input voltage of 2.7V, a load current of 300mA and an
ambient temperature of 70°C. From the typical perfor-
mance graph of switch resistance, the R_DS(ON) of the P-
channel switch at 70°C is approximately 0.94Ω and the
R_DS(ON) of the N-channel synchronous switch is approxi-
mately 0.75Ω.
The series resistance looking into the SW pin is:
R_SW = 0.95Ω (0.51) + 0.75Ω (0.49) = 0.85Ω
Therefore, power dissipated by the part is:
P_D = I_LOAD2 • R_SW = 76.5mW
For the SOT-23 package, the θ_JA is 250°C/ W. Thus, the
junction temperature of the regulator is:
T_J = 70°C + (0.0765)(250) = 89.1°C
which is well below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R_DS(ON)).
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V_OUT immediately shifts by an amount
equal to (∆I_LOAD • ESR), where ESR is the effective series
resistance of C_OUT. ∆I_LOAD also begins to charge or
discharge C_OUT, which generates a feedback error signal.
The regulator loop then acts to return V_OUT to its steady-
state value. During this recovery time V_OUT can be moni-
tored for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3405A-1.375. These items are also illustrated graphi-
cally in Figures 3 and 4. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace and the V_IN trace should be kept short, direct and
wide.
2. Does the (+) plate of C_IN connect to V_IN as closely as
possible? This capacitor provides the AC current to the
internal power MOSFETs.
3. Keep the (–) plates of C_IN and C_OUT as close as possible.
–
V_OUT
+
1
RUN
6
MODE
C_OUT
L1
LTC3405A-1.375
2
GND
5
V_OUT
3
SW
V_IN ⁴
C_IN
V_IN
3405A1375 F03
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 3. LTC3405A-1.375 Layout Diagram
Design Example
As a design example, assume the LTC3405A-1.375 is
used in a single lithium-ion battery-powered cellular phone
application. The V_IN will be operating from a maximum of
4.2V down to about 2.7V. The load current requirement
is a maximum of 0.15A but most of the time it will be in
standby mode, requiring only 2mA. Efficiency at both low
and high load currents is important. Output voltage is
1.375V. With this information we can calculate L using
equation (1),
( )( ) ^{L =}
f
1
∆I_L
⎛
V_{OUT ⎝⎜} 1−
V_OUT
V_IN
⎞
⎠⎟
(3)
10
3405a1375f