LTC2970 Datasheet, PDF (10/36 Pages) Linear Technology – Dual I2C Power Supply Monitor and Margining Controller

LTC2970/LTC2970-1
PI FU CTIO S
V_OUT1 (Pin 12): CH1 Voltage Output. Buffered version of
IDAC1 output voltage.
I_OUT1 (Pin 13): IDAC1 Current Output. Connect a resistor
between this pin and the point-of-load ground for channel
1. The IDAC sources between 0 and 255μA.
I_OUT0 (Pin 14): IDAC0 Current Output. Connect a resistor
between this pin and the point-of-load ground for channel
0. The IDAC sources between 0 and 255μA.
GPIO_1 (Pin 15): General Purpose Input or Open Drain
Digital Output. GPIO_1 can be configured as the IDAC
Fault or Faults output, a digital input, or an open-drain
digital output.
GPIO_0 (Pin 16): General Purpose Input or Open Drain
Digital Output. GPIO_0 can be configured as the voltage
monitor power-good or power-good bar output, a digital
input, or a programmable open-drain output. Power good
is the NOR of all instantaneous OV and UV faults; it does
not include IDAC faults.
⎯A⎯L⎯E⎯R⎯T (Pin 17): Open Drain Digital Output. Connect the
SMBALERT signal to this pin. ^⎯A^⎯L^⎯E^⎯R^⎯T is asserted low when
either IDAC0 or IDAC1 rails out (optional), or when one
of the monitored voltages ventures outside its UV and OV
thresholds (also optional).
SCL (Pin 18): Serial Bus Clock Input.
SDA (Pin 19): Serial Bus Data Input and Output.
GPIO_CFG (Pin 20): GPIO Configuration Digital Input and
Open Drain Output. Pulling GPIO_CFG high will cause the
GPIO_0 and GPIO_1 open-drain outputs to automatically
assert low after a power-on reset. If GPIO_CFG is pulled
low, then GPIO_0 and GPIO_1 do not assert low after
power-up.
ASEL1 (Pin 21): Slave Address Select Bit 1. Tie this pin to
the V_DD pin, ground, or float in order to select the address
location (see Table 2).
ASEL0 (Pin 22): Slave Address Select Bit 0. Tie this pin to
the V_DD pin, ground, or float in order to select the address
location (see Table 2).
REF (Pin 23): Internal Reference Output or ADC Reference
Overdrive Input. The voltage at this pin determines the
full-scale input voltage of the delta-sigma ADC (V_FULL-
SCALE ^{= 6.65 • V}REF^{, typically). An internal 3.5k resistor}
decouples the reference output from this pin. Bypass this
pin to RGND with a 100nF capacitor (C_REF).
RGND (Pin 24): Reference Ground. Connect to device
ground.
GND (Pin 25): Device Ground. Must be soldered to
ground.
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