LTC2460 Datasheet, PDF (10/20 Pages) Linear Technology – Ultra-Tiny, 16-Bit ΔΣ ADCs with 10ppm/°C Max Precision Reference

LTC2460/LTC2462
APPLICATIONS INFORMATION
Table 1. LTC2460/LTC2462 Output Data Format
SINGLE ENDED INPUT V_IN DIFFERENTIAL INPUT VOLTAGE D15 D14 D13 D12...D2 D1
D0
CORRESPONDING
(LTC2460)
V_IN+ – V_IN– (LTC2462)
(MSB)
(LSB) DECIMAL VALUE
≥V_REF
≥V_REF
1
1
1
1
1
1
65535
V_REF – 1LSB
V_REF – 1LSB
1
1
1
1
1
0
65534
0.75 • V_REF
0.75 • V_REF – 1LSB
0.5 • V_REF
0.5 • V_REF – 1LSB
1
1
0
0
0
0
1
0
1
1
1
1
49152
49151
0.5 • V_REF
0
1
0
0
0
0
0
32768
0.5 • V_REF – 1LSB
0.25 • V_REF
–1LSB
–0.5 • V_REF
0
1
1
1
1
1
0
1
0
0
0
0
32767
16384
0.25 • V_REF – 1LSB
–0.5 • V_REF – 1LSB
0
0
1
1
1
1
16383
0
≤ –V_REF
0
0
0
0
0
0
0
The LTC2460 (single-ended input) output code is a direct
binary encoded result, see Table 1.
During the data output operation the CS input pin must
be pulled low (CS = LOW). The data output process starts
with the most significant bit of the result being present at
the SDO output pin (SDO = D15) once CS goes low. A new
data bit appears at the SDO output pin after each falling
edge detected at the SCK input pin. The output data can
be reliably latched on the rising edge of SCK.
Data Input Format
The data input word is 4 bits long and consists of two
enable bits (EN1 and EN2) and two programming bits
(SPD and SLP). EN1 is applied to the first rising edge of
SCK after the conversion is complete. Programming is
enabled by setting EN1 = 1 and EN2 = 0.
The speed bit (SPD) is only used by the LTC2460. In the
default mode, SPD = 0, the output rate is 60Hz and con-
tinuous background offset calibration is not performed. By
changing the SPD bit to 1, background offset calibration is
performed and the output rate is reduced to 30Hz. Alterna-
tively, SDI can be tied directly to ground (SPD = 0) or V_CC
(SPD = 1), eliminating the need to program the device. The
LTC2462 data output rate is always 60Hz and background
offset calibration is performed (SPD = don’t care).
The sleep bit (SLP) is used to power down the on chip
reference. In the default mode, the reference remains
powered up even when the ADC is powered down. If the
SLP bit is set HIGH, the reference will power down after
10
the next conversion is complete. It will remain powered
down until CS is pulled low. The reference startup time is
approximately 12ms. In order to ensure a stable reference
for the following conversions, either the data input/output
time should be delayed 12ms after CS goes low or the
first conversion following a reference start up should be
discarded. If SDI is tied HIGH (LTC2460 operating in 30Hz
mode) the SLP mode is disabled.
Conversion Status Monitor
For certain applications, the user may wish to monitor the
LTC2460/LTC2462 conversion status. This can be achieved
by holding SCK HIGH during the conversion cycle. In
this condition, whenever the CS input pin is pulled low
(CS = LOW), the SDO output pin will provide an indication
of the conversion status. SDO = HIGH is an indication of
a conversion cycle in progress while SDO = LOW is an
indication of a completed conversion cycle. An example
of such a sequence is shown in Figure 5.
Conversion status monitoring, while possible, is not re-
quired for the LTC2460/LTC2462 as its conversion time is
fixed and typically 16.6ms (23ms maximum). Therefore,
external timing can be used to determine the completion of a
conversion cycle.
SERIAL INTERFACE
The LTC2460/LTC2462 transmit the conversion result
and receive the start of conversion command through
a synchronous 2-, 3- or 4-wire interface. This interface
24602f