LTC2224_15 Datasheet, PDF (10/24 Pages) Linear Technology – 12-Bit, 135Msps ADC

LTC2224
W
FUNCTIONAL BLOCK DIAGRA
A_IN+
INPUT
A_IN–
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
V_CM
2.2µF
1.6V
REFERENCE
RANGE
SELECT
REF
SENSE
BUF
SHIFT REGISTER
AND CORRECTION
REFH
REFL INTERNAL CLOCK SIGNALS
DIFFERENTIAL
DIFF
INPUT
CONTROL
REF
LOW JITTER
LOGIC
AMP
CLOCK
DRIVER
REFLB REFHA REFLA REFHB
2.2µF
ENC⁺ ENC^–
M0DE SHDN
OE
0.1µF
0.1µF
1µF
1µF
Figure 1. Functional Block Diagram
OUTPUT
DRIVERS
OV_DD
OF
D11
•
•
•
D0
CLOCKOUT
OGND
2224 F01
2224fa
10