LTC1758-2_15 Datasheet, PDF (10/16 Pages) Linear Technology – RF Power Controllers with 250kHz Control Loop Bandwidth and 40dB Dynamic Range

LTC1758-1/LTC1758-2
APPLICATIO S I FOR ATIO
Determining External Loop Gain and Bandwidth
The external loop voltage gain contributed by the RF chan-
nel and directional coupler network should be measured in
a closed loop configuration. A voltage step is applied to
PCTL and the change in V_PCA (or V_PCB) is measured. The
detected voltage is 0.6 • PCTL for PCTL < 640mV and
1.18PCTL – 0.38V for PCTL > 640mV. The external voltage
gain contributed by the RF power amplifier and directional
coupler network is 0.6 • ∆V_PCTL/∆V_VPCA and (1.18PCTL –
0.38V) • ∆V_PCTL/∆V_PCA. Measuring voltage gain in the
closed loop configuration accounts for the nonlinear de-
tector gain that is dependent on RF input voltage and
frequency.
The LTC1758 unity gain bandwidth specified in the data
sheet assumes that the net voltage gain contributed by the
RF power amplifier and directional coupler is unity. The
bandwidth is calculated by measuring the rise time be-
tween 10% and 90% of the voltage change at V_PCA or V_PCB
for a small step in voltage applied to PCTL.
BW1 = 0.35/rise time
The LTC1758 control amplifier unity gain bandwidth (BW1)
is typically 250kHz. The phase margin of the control
amplifier is typically 90°.
For example, to determine the external RF channel loop
voltage gain with the loop closed, apply a 100mV step to
PCTL from 300mV to 400mV. V_PCA (or V_PCB) will increase
to supply enough feedback voltage to the RF pin to cancel
this 100mV step which would be the required detected
voltage of 60mV. V_PCA changed from 1.498V to 1.540V to
create the RF output power change required. The net
external voltage gain contributed by the RF power ampli-
fier and directional coupler network can be calculated by
dividing the 60mV change at the RF pin by the 42mV
change at the V_PCA pin. The net external voltage gain would
then be approximately 1.4. The loop bandwidth extends to
1.4␣ • BW1. If BW1 is 250kHz, the loop bandwidth in-
creases to approximately 350kHz. The phase margin is
extracted from Figure 3. Repeat the above voltage gain
measurement over the full power and frequency range.
The phase margin degradation, due to external and inter-
nal pole combinations, is difficult to determine since
complex poles are present. Gain peaking may occur,
resulting in higher bandwidth and lower phase margin
than predicted from the open loop Bode plot. A low
frequency AC SPICE model of the LTC1758 power control-
ler is included to better determine pole and zero interac-
tions. The user can apply external gains and poles to
determine bandwidth and phase margin. DC, transient and
RF information cannot be extracted from the present
model. The model is suitable for external gain evaluations
up to 6×. The 350kHz PCTL input filter limits the band-
width, therefore, use the RF input as demonstrated in the
model.
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
100
140
R_LOAD = 2k
130
C_LOAD = 33pF ₁₂₀
110
PHASE
100
90
80
70
GAIN
60
50
40
30
20
10
0
1k 10k 100k 1M 10M
FREQUENCY (Hz)
1758 F03
Figure 3. Measured Open Loop Gain and Phase, PCTL < 640mV
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
100
150
R_LOAD = 2k
140
C_LOAD = 33pF ₁₃₀
120
110
PHASE
100
90
80
GAIN
70
60
50
40
30
20
10
1k
10k 100k 1M 10M
FREQUENCY (Hz)
1758 F04
Figure 4. Measured Open Loop Gain and Phase, PCTL > 640mV
10