LTC1288_15 Datasheet, PDF (10/24 Pages) Linear Technology – 3V Micropower Sampling 12-Bit A/D Converters in SO-8 Packages

LTC1285/LTC1288
APPLICATION INFORMATION
OVERVIEW
The LTC1285 and LTC1288 are 3V micropower, 12-bit,
successive approximation sampling A/D converters. The
LTC1285 typically draws 160µA of supply current when
sampling at 7.5kHz while the LTC1288 nominally con-
sumes 210µA of supply current when sampling at 6.6 kHz.
The extra 50µA of supply current on the LTC1288 comes
from the reference input which is intentionally tied to the
supply. Supply current drops linearly as the sample rate is
reduced (see Supply Current vs Sample Rate). The ADCs
automatically power down when not performing conver-
sions, drawing only leakage current. They are packaged in
8-pin SO and DIP packages. The LTC1285 and LTC1288
operate on a single supply from 2.7V to 6V.
Both the LTC1285 and the LTC1288 contain a 12-bit,
switched-capacitor ADC, a sample-and-hold, and a serial
port (see Block Diagram). Although they share the same
basic design, the LTC1285 and LTC1288 differ in some
respects. The LTC1285 has a differential input and has an
external reference input pin. It can measure signals float-
ing on a DC common-mode voltage and can operate with
reduced spans to 1.5V. Reducing the spans allows it to
achieve 366µV resolution. The LTC1288 has a two-chan-
nel input multiplexer and can convert either channel with
respect to ground or the difference between the two. The
reference input is tied to the supply pin.
SERIAL INTERFACE
The 2-channel LTC1288 communicates with micropro-
cessors and other external circuitry via a synchronous,
half duplex, 4-wire serial interface. The single channel
LTC1285 uses a 3-wire interface (see Operating Sequence
in Figures 1 and 2).
t_CYC
CS
t_suCS
CLK
POWER
DOWN
D_OUT
CS
HI-Z ^NULL
BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
HI-Z
t_SMPL
(MSB)
t_CONV
t_DATA
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY.
t_CYC
NULL
BIT B11 B10 B9 B8
t_suCS
CLK
POWER DOWN
D_OUT
NULL
HI-Z
BIT
B11 B10 B9 B8 B7
B6 B5 B4 B3 B2
B1 B0 B1 B2 B3 B4 B5
B6 B7 B8
B9 B10 B11*
HI-Z
t_SMPL
(MSB)
t_CONV
t_DATA
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY.
t_DATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT
BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
LTC1285/88 • F01
Figure 1. LTC1285 Operating Sequence
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