LTC1287_15 Datasheet, PDF (10/16 Pages) Linear Technology – 3V Single Chip 12-Bit Data Acquisition System

LTC1287
APPLICATI S I FOR ATIO
“+” Input Settling
The input capacitor is switched onto the “+” input during
the sample phase (t_SMPL, see Figures 8a, 8b and 8c). The
sample period can be as short as t_WHCS + 0.5 CLK cycle or
as long as t_WHCS + 1.5 CLK cycles before a conversion
starts. This variability depends on where CS falls relative
to CLK. The voltage on the “+” input must settle completely
within the sample period. Minimizing R_SOURCE+ and C1
will improve the settling time. If large “+” input source
resistance must be used, the sample time can be increased
by using a slower CLK frequency. With the minimum
possible sample time of 6.0µs, R_SOURCE+ < 4.0k and C1
< 20pF will provide adequate settle time.
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figures 8a,
8b and 8c). During the conversion, the “+” input voltage is
“+” and “–” Input Settling Windows
t_WHCS
CS
CLK
D_OUT
(+) INPUT
(–) INPUT
CS
t_SUCS
t_SMPL
(+) INPUT MUST SETTLE DURING THIS TIME
B11
HI-Z
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
B10
B9
Figure 8a. Setup Time (t_SUCS) is Met
t_WHCS
LTC1287 F8a
CLK
D_OUT
(+) INPUT
(–) INPUT
10
t_SMPL
(+) INPUT MUST SETTLE DURING THIS TIME
HI-Z
B11
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
B10
B9
Figure 8b. Setup Time (t_SUCS) is Met
LTC1287 F8b
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