LT6554 Datasheet, PDF (10/12 Pages) Linear Technology – 650MHz Gain of 1 Triple Video Buffer

LT6554
TYPICAL APPLICATIO
RGB Buffer Demo Board
The DC794 Demo Board illustrates optimal routing,
bypassing and termination using the LT6554 as an
RGB video buffer. The schematic is shown in Figure 4. All
inputs and outputs are routed to have a characteristic
impedance of 75Ω. The 75Ω input shunt and output series
terminations are connected as close to the part as pos-
sible. While the 75Ω back termination resistors at the
outputs of the LT6554 minimize signal reflections in the
output traces and isolate the part from any capacitive
loading in those traces, they also contribute to gain error
if the output is not terminated with high impedance. For
example, if the output is terminated with a 1k load, the 75Ω
back termination will cause a 7% gain error. Decreasing
the value of the back termination resistors will decrease
the signal attenuation but may compromise the AC re-
sponse. However, connecting the LT6554 outputs to the
output traces on the DC794 board without some series
resistance is not recommended; 10Ω to 20Ω is generally
sufficient.
A fourth signal trace is provided at the bottom of the
DC794 demo board with dimensions identical to the
E1
EN
combined input and output of the other channels. This
trace can be used for calibrating the effects of electrical
delay and impedance mismatching and is not necessary
in an end-user application. Jumpers and additional con-
nectors are also included to allow for evaluation of the
enable feature and single supply operation.
RGB Video Selector/Cable Driver
A video multiplexer can be implemented using the EN pins
of parallel LT6554s as shown in Figure 5. In this applica-
tion, the corresponding outputs are connected together
and one LT6554 is switched on while the other is switched
off. A fast inverter provides a complementary signal to
ensure that only one set of R, G and B channels is buffered
at any time.
Since the output impedance of a disabled LT6554 is very
high, adding additional channels will not resistively load
an enabled output. However, since the disabled LT6554
has around 6pF of capacitance, it may be desirable to
resistively isolate the outputs of each channel to maintain
flat frequency response as shown in the graph labeled
“Maximum Capacitive Load vs Output Series Resistor” in
the Typical Performance Characteristics section.
J1
50Ω BNC
1
EN
5432
JP1
CONTROL
12 3
ENABLE EXT
JP2
DGND
12 3
E2
AGND FLOAT DGND
5 ^{BNC × 3}
INR 4
1 Z = 75
3
2 J5
5
ING 4
Z = 75
1
3
2 J6
5
Z = 75
INB 4
1
3
2 J7
R4
R5
R6
75Ω 75Ω 75Ω
1
EN
LT6554
V^{+ 16}
2
DGND
V^{+ 15}
3
INR
14
OUTR
4 _AGND
V^{– 13}
5 _ING
OUTG ¹²
6 _AGND
V^{+ 11}
7
INB
10
OUTB
8 _V–
V^{– 9}
C1
4700pF
C2
470pF
C3
4700pF
V⁺
V⁺
C4
J2
10µF, 16V BANANA
1210
JACK
R1
75Ω
Z = 75
BNC x3 ₅
1
4
OUTR
3
R2
J9 2
75Ω
Z = 75
5
1
4 OUTG
R3
75Ω
Z = 75
3
J10 2
5
1
4 OUTB
3
J11 2
E3
AGND
V^–
V^–
AGND
J3
BANANA
5 ^JACK
CAL 4
1
3
2 J8
BNC
SINGLE DUAL
1 ²³
JP3
SUPPLY
C5
470pF
C6
1000pF
C7
470pF
C8
4700pF
C9
10µF, 16V
1210
J4
BANANA JACK
Figure 4. DC794 Demo Board Schematic
Z = 75
ALL BNC: CANARE BCJ-BPLH
5
1
4
3
J12 2
BNC
CAL
6554 F04
6554fa
10